This book presents extended and revised versions of the best papers that were presented during the twelfth edition of the IFIP TC10 Working Group 10.5 International Conference on Very Large Scale Integration. The purpose of this conference was to provide a forum to exchange ideas and show research results in the field of microelectronics design. The current trend toward increasing chip integration brings about exhilarating new challenges both at the physical and system-design levels. This book aims to address these exciting issues.
Author(s): Manfred Glesner, Ricardo Reis, Leandro Indrusiak, Vincent Mooney, Hans Eveking
Edition: 1
Publisher: Springer
Year: 2006
Language: English
Commentary: 51025
Pages: 315
VLSI-SOC: From Systems to Chips......Page 1
Contents......Page 6
Preface......Page 9
Effect of Power Optimizations on Soft Error Rate......Page 11
Dynamic Models for Substrate Coupling in Mixed-Mode Systems......Page 31
Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs......Page 48
Automated Conversion of SystemC Fixed-Point Data Types......Page 64
Exploration of Sequential Depth by Evolutionary Algorithms......Page 82
Validation of Asynchronous Circuit Specifications Using IF/CADP......Page 93
On-Chip Property Verification Using Assertion Processors......Page 109
Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems......Page 126
A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications......Page 140
Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans......Page 155
Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures......Page 171
Optimizing SOC Test Resources Using Dual Sequences......Page 186
A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits......Page 202
Low Power Java Processor for Embedded Applications......Page 217
Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes......Page 233
Evaluation Methodology for Single Electron Encoded Threshold Logic Gates......Page 250
Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath......Page 266
Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths......Page 283
Stuck-At-Fault Testability of SPP Three-Level Logic Forms......Page 300
Authors Index......Page 315
