VLSI design of wavelet transform : analysis, architecture and design analysis

Contents......Page 12
Preface......Page 8
1.1.1 DCT-based block coding......Page 19
1.1.2 DWT-based bit-plane coding......Page 20
1.2.1 Close-loop motion-compensated prediction......Page 22
1.2.2 Open-loop motion-compensated temporal filtering......Page 23
1.3.1.1 Computation analysis......Page 25
1.3.1.2 Data access analysis......Page 26
1.4 Book Outline......Page 28
2.1.1 Properties of a multi-resolution transform......Page 31
2.1.2 The pyramid structure of discrete multi-resolution representation......Page 33
2.1.3 The wavelet decomposition......Page 35
2.1.4 The pyramid structure of computing wavelet transform......Page 38
2.1.5 Inverse wavelet transform......Page 40
2.1.6 2-D wavelet transform......Page 43
2.2 Polyphase decomposition......Page 45
2.3 Lifting Scheme......Page 49
2.3.1 Lifting steps for wavelet transform......Page 50
2.3.2 The Euclidean algorithm......Page 52
2.3.3 The lifting factorization algorithm......Page 54
2.4 B-spline formulation......Page 60
2.5 Classification of 1-D DWT Algorithms......Page 62
2.6 Algorithms of 2-D DWT......Page 63
2.7 Image Coding Using 2-D DWT......Page 66
3.1 Convolution-Based Architectures......Page 71
3.2.1 Direct implementation of lifting scheme......Page 73
3.2.2 Flipping structure......Page 77
3.2.3 Design example of JPEG 2000 default (9 7) filter......Page 79
3.2.4 Design example of integer (9 7) filter......Page 82
3.2.5 Design example of linear (6 10) filter......Page 84
3.3.1 B-spline factorized architectures for DWT and IDWT......Page 85
3.3.2.1 Direct implementation of B-spline part......Page 89
3.3.3 Design example of JPEG 2000 default (9 7) DWT filter......Page 90
3.3.4.1 Comparison......Page 93
3.3.4.2 Detailed gate count comparison......Page 96
3.3.5 Design example of linear (10 18) DWT filter......Page 97
3.3.6 Design example of linear (10 18) IDWT filter......Page 99
3.4 General Performance Analysis......Page 100
3.4.1 Multipliers and adders......Page 103
3.4.2 Critical path and registers......Page 104
3.5 Wordlength Analysis in Single-Level 1-D DWT......Page 105
3.5.1 Dynamic range analysis for single-level 1-D DWT......Page 107
3.5.1.2 Dynamic range analysis for single level 1-D DWT......Page 108
3.5.2 Round-off noise analysis basics for single level 1-D DWT......Page 109
4.1 Introduction......Page 113
4.2.1 Direct scan......Page 114
4.2.2 Row-column-column-row scan......Page 115
4.2.3 Line-based scan......Page 116
4.2.3.1 Data flow for data buffer of size 1.5N......Page 119
4.2.4.1 1-level line-based architecture......Page 121
4.2.4.2 Multi-level line-based architecture......Page 124
4.2.5 Non-overlapped and overlapped block-based scans......Page 125
4.2.7 Comparison of scan methods for 1-level 2-D DWT architectures......Page 127
4.2.8 Summary......Page 128
4.3.1 Systolic-parallel and parallel-parallel architectures......Page 130
4.3.3 Generic 1-level line-based architecture......Page 131
4.3.4 Generic multi-level line-based architecture......Page 133
4.3.4.1 Adopting two 1-D DWT modules (2DWTM)......Page 134
4.3.4.2 Adopting three 1-D DWT modules (3DWTM)......Page 135
4.3.5.1 General case......Page 137
4.4 Line Buffer Wordlength Analysis for Line-Based 2-D DWT......Page 138
4.4.1 Background to wordlength analysis in line-based DWT......Page 140
4.4.2.2 LL-band dynamic range analysis......Page 142
4.4.2.4 The combined dynamic range analysis methodology......Page 144
4.4.3.2 Noise power model of single-level 1-D DWT......Page 146
4.4.3.4 Noise power analysis in reconstructed image......Page 147
4.4.4 Experimental results......Page 148
4.5 On-Chip Memory Implementation Issues......Page 150
4.5.2 Schemes to reduce memory bandwidth......Page 151
4.5.2.1 Reducing average memory bandwidth using parallel processing......Page 152
4.5.2.2 Two-lifting scheme......Page 153
4.5.2.3 N-lifting scheme......Page 154
4.5.3.1 M-scan for two-lifting scheme......Page 156
4.5.3.2 M-scan for N-lifting scheme......Page 157
4.5.4 Experimental results......Page 159
4.5.5 Summary......Page 160
5.1 Introduction to JPEG 2000 Algorithm......Page 161
5.1.1 Coding system overview......Page 162
5.1.2 Discrete wavelet transform......Page 163
5.1.2.2 9-7 irreversible filter......Page 164
5.1.3 Embedded block coding......Page 165
5.1.4 Rate-distortion optimization......Page 167
5.1.5 Coding efficiency of JPEG 2000......Page 169
5.2 Design Issues of JPEG 2000 Encoding Systems......Page 173
5.2.1 Discrete wavelet transform......Page 174
5.2.3 Rate-distortion optimization......Page 175
5.3.1 Preliminary......Page 176
5.3.2 System architecture......Page 177
5.3.3 Discrete wavelet transform......Page 178
5.3.4 Embedded block coding......Page 179
5.3.5 Scheduling......Page 180
5.3.6.1 Performance and chip feature......Page 182
5.3.7 Summary......Page 184
5.4 Stripe Pipelined Scheme and the Corresponding DWT Architecture......Page 185
5.4.1 Preliminary......Page 186
5.4.2 System architecture......Page 187
5.4.2.1 Stripe pipeline scheme......Page 188
5.4.2.2 Level switch DWT......Page 189
5.4.2.3 Memory requirement for LS-DWT......Page 192
5.4.2.4 Code-block switch EBC......Page 193
5.4.3.1 Memory reduction......Page 194
5.4.3.2 Comparison......Page 195
5.5 Summary......Page 196
6.1 Convolution-Based MCTF......Page 199
6.2 Lifting-Based MCTF......Page 201
6.3.1 Prediction stage......Page 203
6.3.2 Update stage......Page 205
6.4 Different MCTF Schemes with DWT for Video Coding......Page 206
6.4.1 Multi-level MCTF scheme......Page 207
6.4.2 In-band MCTF scheme......Page 210
6.4.3 Hybrid MCTF scheme......Page 211
6.5 Pyramid MCTF with DCT for Video Coding......Page 212
6.6 Scalable Video Coding......Page 215
7.1 The Concept of Motion Estimation and Compensation......Page 219
7.2 Block Matching Algorithm......Page 220
7.2.1 Full search algorithm......Page 222
7.2.2.1 Partial distortion elimination......Page 223
7.2.2.2 Successive elimination algorithm......Page 224
7.2.3.1 Simplification of matching criterion......Page 225
7.2.3.2 Reduction on search candidates......Page 226
7.2.3.3 Predictive search......Page 229
7.2.3.4 Hierarchical search......Page 230
7.2.4 Summary......Page 231
7.3 Architecture of Motion Estimation......Page 232
7.3.1.1 Inter-level architecture......Page 233
7.3.1.2 Intra-level architecture......Page 236
7.3.2 Architecture for fast full search and fast search algorithms......Page 238
7.3.2.1 Tree-based architecture......Page 239
7.3.2.3 Architecture for three step search......Page 242
7.3.3 Block-level data re-use scheme......Page 243
7.3.3.1 Redundancy access factor......Page 244
7.3.3.3 Level B scheme......Page 245
7.3.3.4 Level C scheme......Page 246
7.3.3.6 Level C+ scheme......Page 247
7.4 Summary......Page 250
8.1 Memory Access in MCTF......Page 253
8.1.1 Redundancy access factor for ME......Page 254
8.1.2 Redundancy access factor for MC......Page 255
8.2.1 The architecture for MCTF......Page 257
8.2.2.1 Direct implementation......Page 258
8.2.2.2 Double Reference Frames (DRF)......Page 259
8.2.2.3 Double Current Frames (DCF)......Page 260
8.2.2.4 Modified Double Current Frames (m-DCF)......Page 261
8.2.2.5 Comparison......Page 262
8.2.2.6 Extension......Page 264
8.2.3 Memory analysis for update stage......Page 267
8.2.4 Memory analysis of one-level MCTF......Page 268
8.3.1.1 Decomposition level......Page 270
8.3.1.3 Update stage......Page 272
8.3.2.1 Computational complexity......Page 274
8.3.2.3 External memory size......Page 275
8.3.2.4 Coding delay......Page 276
8.4 Case Study......Page 279
8.5 Rate-Distortion-Computation Scalability......Page 280
8.6 Analysis of Pyramid MCTF......Page 282
8.6.1 Computation complexity......Page 283
8.6.3 External memory storage......Page 284
8.7 Conclusion......Page 285
Bibliography......Page 287
Index......Page 299