Transactions on HiPEAC is a new journal which aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems.
This inaugural issue contains 21 papers - headed by an article by Sir Maurice Wilkes, who provides a perspective on the exciting evolution of computers to the present day. Reflecting on the evolution in computer architecture over the last decades, he also provides his outlook on the forces that will be important for developments over the next decade. The second regular paper describes a roadmap put together by the HiPEAC community to mark out the 10 most important research challenges to be faced in the next decade. The volume also includes a part containing the best papers of the 2005 International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2005), a part consisting of papers devoted to the topic of optimizing compilers, as well as a third part containing the best papers on embedded architectures and compilers from the 2006 ACM International Conference on Computing Frontiers.
Author(s): Maurice V. Wilkes (auth.), Per Stenström (eds.)
Series: Lecture Notes in Computer Science 4050
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2007
Language: English
Pages: 368
Tags: Arithmetic and Logic Structures; Processor Architectures; Input/Output and Data Communications; Logic Design; Computer Communication Networks; Programming Languages, Compilers, Interpreters
Front Matter....Pages -
High Performance Processor Chips....Pages 1-4
High-Performance Embedded Architecture and Compilation Roadmap....Pages 5-29
Front Matter....Pages 31-31
Introduction to Part 1....Pages 33-33
Quick and Practical Run-Time Evaluation of Multiple Program Optimizations....Pages 34-53
Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems....Pages 54-73
GCH: Hints for Triggering Garbage Collections....Pages 74-94
Memory-Centric Security Architecture....Pages 95-115
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems....Pages 116-135
Front Matter....Pages 137-137
Introduction to Part 2....Pages 139-139
Convergent Compilation Applied to Loop Unrolling....Pages 140-158
Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations....Pages 159-178
Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures....Pages 179-193
Automatic Discovery of Coarse-Grained Parallelism in Media Applications....Pages 194-213
An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors....Pages 214-233
Front Matter....Pages 235-235
Introduction to Part 3....Pages 237-238
Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology....Pages 239-258
Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture....Pages 259-278
Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors....Pages 279-297
Selective Code Compression Scheme for Embedded Systems....Pages 298-316
A Prefetching Algorithm for Multi-speed Disks....Pages 317-340
Front Matter....Pages 235-235
Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation....Pages 341-360
Back Matter....Pages -
