Analog CMOS integrated circuits are in widespread use for communications, entertainment, multimedia, biomedical, and many other applications that interface with the physical world. Although analog CMOS design is greatly complicated by the design choices of drain current, channel width, and channel length present for every MOS device in a circuit, these design choices afford significant opportunities for optimizing circuit performance.This book addresses tradeoffs and optimization of device and circuit performance for selections of the drain current, inversion coefficient, and channel length, where channel width is implicitly considered. The inversion coefficient is used as a technology independent measure of MOS inversion that permits design freely in weak, moderate, and strong inversion. This book details the significant performance tradeoffs available in analog CMOS design and guides the designer towards optimum design by describing:An interpretation of MOS modeling for the analog designer, motivated by the EKV MOS model, using tabulated hand expressions and figures that give performance and tradeoffs for the design choices of drain current, inversion coefficient, and channel length; performance includes effective gate-source bias and drain-source saturation voltages, transconductance efficiency, transconductance distortion, normalized drain-source conductance, capacitances, gain and bandwidth measures, thermal and flicker noise, mismatch, and gate and drain leakage currentMeasured data that validates the inclusion of important small-geometry effects like velocity saturation, vertical-field mobility reduction, drain-induced barrier lowering, and inversion-level increases in gate-referred, flicker noise voltageIn-depth treatment of moderate inversion, which offers low bias compliance voltages, high transconductance efficiency, and good immunity to velocity saturation effects for circuits designed in modern, low-voltage processesFabricated design examples that include operational transconductance amplifiers optimized for various tradeoffs in DC and AC performance, and micropower, low-noise preamplifiers optimized for minimum thermal and flicker noiseA design spreadsheet, available at the book web site, that facilitates rapid, optimum design of MOS devices and circuits Tradeoffs and Optimization in Analog CMOS Design is the first book dedicated to this important topic. It will help practicing analog circuit designers and advanced students of electrical engineering build design intuition, rapidly optimize circuit performance during initial design, and minimize trial-and-error circuit simulations.
Author(s): David Binkley
Edition: 1
Year: 2008
Language: English
Pages: 632
Tradeoffs and Optimization in Analog CMOS Design......Page 3
Contents......Page 9
Foreword......Page 19
Preface......Page 23
Acknowledgments......Page 25
List of Symbols and Abbreviations......Page 27
1.1 Importance of Tradeoffs and Optimization in Analog CMOS Design......Page 39
1.2 Industry Designers and University Students as Readers......Page 40
1.3 Organization and Overview of Book......Page 41
1.4 Full or Selective Reading of Book......Page 43
1.6 Limitations of the Methods......Page 44
1.7 Disclaimer......Page 45
PART I MOS Device Performance, Tradeoffs and Optimization for Analog CMOS Design......Page 47
2.1 Introduction......Page 49
2.3 Bipolar Transistor Collector Current and Transconductance......Page 50
2.4.1 In Weak Inversion......Page 51
2.4.2 In Strong Inversion without Velocity Saturation Effects......Page 52
2.4.3 In Strong Inversion with Velocity Saturation Effects......Page 54
2.4.4 In Moderate Inversion and All Regions of Operation......Page 56
2.5 MOS Drain–Source Conductance......Page 61
2.6.1 Electronic Design Automation Tools......Page 63
2.6.2 Design Methods......Page 66
2.6.3 Previous Application of Design Methods Presented in this Book......Page 67
References......Page 68
3.1 Introduction......Page 71
3.2 Advantages of Selecting Drain Current, Inversion Coefficient, and Channel Length in Analog CMOS Design......Page 72
3.2.2 Design in Moderate Inversion......Page 73
3.2.5 Simple Predictions of Performance and Trends......Page 74
3.2.7 Observing Performance Tradeoffs – The MOSFET Operating Plane......Page 75
3.2.8 Cross-Checking with Computer Simulation MOS Models......Page 77
3.3.1 Calculation of Composite Process Parameters......Page 78
3.3.2 DC, Small-Signal, and Intrinsic Gate Capacitance Parameters......Page 80
3.3.3 Flicker Noise and Local-Area DC Mismatch Parameters......Page 82
3.3.4 Gate-Overlap and Drain–Body Capacitance Parameters......Page 83
3.4 Substrate Factor and Inversion Coefficient......Page 84
3.4.1 Substrate Factor......Page 85
3.4.2.1 Traditional inversion coefficient......Page 88
3.4.2.2 Fixed–normalized inversion coefficient......Page 89
3.4.2.3 Using the fixed–normalized inversion coefficient in design......Page 90
3.4.2.4 Regions and subregions of inversion......Page 91
3.5.1 Bandgap Energy, Thermal Voltage, and Substrate Factor......Page 93
3.5.2 Mobility, Transconductance Factor, and Technology Current......Page 95
3.5.3 Inversion Coefficient......Page 97
3.5.5 Design Considerations......Page 98
3.6 Sizing Relationships......Page 99
3.6.1 Shape Factor......Page 100
3.6.2 Channel Width......Page 102
3.6.3 Gate Area and Silicon Cost......Page 103
3.7.1 Drain Current......Page 105
3.7.1.1 Without small-geometry effects......Page 106
3.7.1.2 With velocity saturation effects......Page 108
3.7.1.4 With velocity saturation and VFMR effects......Page 110
3.7.1.5 The equivalent velocity saturation voltage......Page 113
3.7.1.6 Predicted and measured values......Page 114
3.7.1.7 The extrapolated threshold voltage......Page 117
3.7.2.1 Without small-geometry effects......Page 118
3.7.2.2 With velocity saturation and VFMR effects......Page 120
3.7.2.3 Predicted and measured values......Page 124
3.7.2.4 Summary of trends......Page 126
3.7.3.1 Physical versus circuit definition......Page 127
3.7.3.2 Without small-geometry effects......Page 128
3.7.3.3 With velocity saturation effects......Page 130
3.7.3.4 Predicted and measured values......Page 134
3.7.3.5 Summary of trends......Page 135
3.8.1 Small-Signal Model and its Application......Page 136
3.8.2.1 Without small-geometry effects......Page 141
3.8.2.2 With velocity saturation and VFMR effects......Page 144
3.8.2.3 Predicted and measured values......Page 149
3.8.2.4 Summary of trends......Page 151
3.8.2.6 Distortion......Page 153
3.8.3 Body-Effect Transconductance and Relationship to Substrate Factor......Page 159
3.8.3.1 Substrate factor......Page 160
3.8.3.2 Body-effect transconductance......Page 163
3.8.3.3 Predicted and measured values......Page 164
3.8.3.4 Summary of trends......Page 167
3.8.4 Drain Conductance......Page 168
3.8.4.1 Due to channel length modulation......Page 169
3.8.4.2 Due to DIBL......Page 179
3.8.4.3 Due to hot-electron effects......Page 184
3.8.4.4 Impact of increase near VDS,sat......Page 188
3.8.4.5 Measured values......Page 190
3.8.4.6 Summary of trends......Page 199
3.8.5 Intrinsic Voltage Gain......Page 201
3.9.1 Gate-Oxide Capacitance......Page 207
3.9.2 Intrinsic Gate Capacitances......Page 208
3.9.3 Extrinsic Gate-Overlap Capacitances......Page 211
3.9.4 Drain–Body and Source–Body Junction Capacitances......Page 214
3.9.6 Intrinsic Bandwidth......Page 217
3.9.7 Extrinsic and Diode-Connected Bandwidths......Page 223
3.10 Noise......Page 226
3.10.1 Thermal Noise in the Ohmic Region......Page 227
3.10.2.1 Without small-geometry effects......Page 228
3.10.2.2 With small-geometry effects......Page 231
3.10.2.3 Summary of drain-referred and gate-referred thermal noise......Page 232
3.10.3 Flicker Noise......Page 238
3.10.3.1 Carrier density fluctuation model......Page 239
3.10.3.2 Carrier mobility fluctuation model......Page 241
3.10.3.3 Unified, carrier density, correlated mobility fluctuation model......Page 242
3.10.3.4 Flicker-noise prediction from flicker-noise factors......Page 245
3.10.3.5 Reported flicker-noise factors and trends......Page 247
3.10.3.6 Measured and predicted flicker noise......Page 250
3.10.3.7 Summary of gate-referred and drain-referred flicker noise......Page 255
3.10.3.8 Flicker-noise corner frequency......Page 262
3.10.4 Gate, Substrate, and Source Resistance Thermal Noise......Page 265
3.10.6 Induced Gate Noise Current......Page 267
3.10.7 Gate Leakage Noise Current......Page 269
3.11.1.1 Modeling......Page 271
3.11.1.2 Reported mismatch factors and trends......Page 275
3.11.1.3 Edge effects and other model limitations......Page 277
3.11.1.4 Calculating gate–source voltage and drain current mismatch......Page 279
3.11.1.5 Threshold-voltage mismatch increase for non-zero VSB......Page 282
3.11.1.6 Threshold-voltage dominance of mismatch......Page 284
3.11.1.7 Summary of gate–source voltage and drain current mismatch......Page 285
3.11.2.1 Modeling......Page 292
3.11.2.2 Reported mismatch factors and trends......Page 293
3.11.2.3 Gate–source voltage and drain current mismatch......Page 294
3.11.2.5 Critical spacing for comparable distance and local-area mismatch......Page 296
3.11.3.1 Bandwidth, power, and accuracy tradeoffs in current-mode circuits......Page 297
3.11.3.2 Bandwidth, power, and accuracy tradeoffs in voltage-mode circuits......Page 300
3.11.3.3 Timing skew in digital circuits......Page 302
3.11.4.1 Transconductance mismatch......Page 303
3.11.4.2 Drain–source conductance mismatch......Page 305
3.12.1 Gate Leakage Current and Conductance......Page 306
3.12.1.1 Gate current......Page 307
3.12.1.2 Gate conductance......Page 311
3.12.2.1 Minimum frequency of operation......Page 312
3.12.2.2 Intrinsic current gain......Page 313
3.12.2.3 Discharge of capacitances......Page 314
3.12.2.5 Mismatch......Page 315
3.12.2.6 Summary of tradeoffs......Page 316
3.12.3 Drain–Body and Source–Body Leakage Current......Page 317
3.12.4 Subthreshold Drain Leakage Current......Page 320
References......Page 321
4.1 Introduction......Page 333
4.2.1 Exploring Drain Current, Inversion Coefficient, and Channel Length Separately......Page 334
4.2.2 Trends as Inversion Coefficient Increases......Page 335
4.2.3 Trends as Channel Length Increases......Page 338
4.2.4 Trends as Drain Current Increases......Page 340
4.3.1 Overview – The MOSFET Operating Plane......Page 341
4.3.2 Region and Level of Inversion – The Inversion Coefficient as a Number Line......Page 342
4.3.3 Tradeoffs Common to All Devices......Page 344
4.3.3.1 Channel width and gate area......Page 347
4.3.3.2 Intrinsic gate capacitance and drain–body capacitance......Page 348
4.3.3.3 Effective gate–source voltage and drain–source saturation voltage......Page 350
4.3.3.4 Transconductance efficiency and Early voltage......Page 352
4.3.3.5 Intrinsic voltage gain and bandwidth......Page 355
4.3.4.1 Transconductance distortion......Page 358
4.3.4.2 Intrinsic gate capacitance and gate-referred thermal-noise voltage......Page 361
4.3.4.3 Gate-referred flicker-noise voltage and gate–source mismatch voltage......Page 363
4.3.5 Tradeoffs Specific to Current-Mirror Devices......Page 366
4.3.5.1 Intrinsic bandwidth and drain-referred thermal-noise current......Page 367
4.3.5.2 Drain-referred flicker-noise current and drain mismatch current......Page 371
4.3.6 Tradeoffs in Figures of Merit......Page 374
4.3.6.2 Intrinsic voltage gain, bandwidth, and gain–bandwidth......Page 376
4.3.6.3 Transconductance efficiency and intrinsic bandwidth......Page 377
4.3.6.5 Bandwidth, power, and accuracy with DC offset......Page 378
4.3.6.6 Bandwidth, power, and accuracy with thermal noise......Page 380
4.3.6.8 Extensions......Page 383
4.4 Design of Differential Pairs and Current Mirrors Using the Analog CMOS Design, Tradeoffs and Optimization Spreadsheet......Page 384
4.4.1 Selecting Inversion Coefficient......Page 386
4.4.2 Selecting Channel Length......Page 391
4.4.3 Selecting Drain Current......Page 397
4.4.4 Optimizing for DC, Balanced, and AC Performance......Page 401
4.4.4.1 DC optimization......Page 402
4.4.4.3 Balanced optimization......Page 404
4.4.4.4 Optimizations at millipower operation......Page 405
4.4.4.5 Optimizations at micropower operation......Page 407
4.4.5 Summary Procedure for Device Optimization......Page 410
References......Page 411
PART II Circuit Design Examples Illustrating Optimization for Analog CMOS Design......Page 413
5.1 Introduction......Page 415
5.2.1 Simple OTAs......Page 417
5.2.2 Cascoded OTAs......Page 418
5.3 Circuit Analysis and Performance Optimization......Page 420
5.3.1.1 Simple OTAs......Page 421
5.3.1.3 Optimization......Page 422
5.3.2.2 Cascoded OTAs......Page 423
5.3.3.1 Simple OTAs......Page 425
5.3.3.3 Optimization......Page 426
5.3.4.1 Simple OTAs......Page 427
5.3.4.2 Cascoded OTAs......Page 429
5.3.4.3 Optimization......Page 430
5.3.5.1 Simple OTAs......Page 431
5.3.5.2 Cascoded OTAs......Page 432
5.3.5.3 Optimization......Page 434
5.3.6.1 Simple OTAs......Page 435
5.3.6.2 Cascoded OTAs......Page 437
5.3.6.3 Optimization......Page 438
5.3.7.1 Simple OTAs......Page 441
5.3.7.2 Cascoded OTAs......Page 445
5.3.7.3 Optimization......Page 447
5.3.8 Systematic Offset Voltage for Simple OTAs......Page 450
5.3.9.1 Simple OTAs......Page 451
5.3.9.2 Cascoded OTAs......Page 453
5.3.9.3 Optimization......Page 454
5.3.11.1 Simple OTAs......Page 455
5.3.11.2 Cascoded OTAs......Page 457
5.3.11.3 Optimization......Page 459
5.3.12.2 Cascoded OTAs......Page 461
5.3.13 Management of Small-Geometry Effects......Page 462
5.4.1 Selection of MOSFET Inversion Coefficients and Channel Lengths......Page 463
5.4.1.1 DC optimization......Page 467
5.4.1.2 AC optimization......Page 468
5.4.2 Predicted and Measured Performance......Page 469
5.4.2.1 Transconductance, output resistance, and voltage gain......Page 473
5.4.2.3 Thermal noise......Page 477
5.4.2.4 Flicker noise......Page 478
5.4.2.5 Offset voltage due to local-area mismatch......Page 479
5.4.2.8 Slew rate......Page 480
5.4.2.10 Input, 1 dB compression voltage......Page 481
5.4.2.11 Layout area......Page 482
5.4.2.12 Tradeoffs in DC accuracy, low-frequency AC accuracy, voltage gain, and transconductance bandwidth......Page 484
5.4.3 Other Optimizations: Ensuring Input Devices Dominate Thermal Noise......Page 485
5.5.1 Selection of MOSFET Inversion Coefficients and Channel Lengths......Page 486
5.5.1.1 DC optimization......Page 489
5.5.1.2 AC optimization......Page 490
5.5.2 Predicted and Measured Performance......Page 491
5.5.2.1 Transconductance, output resistance, and voltage gain......Page 496
5.5.2.2 Frequency response......Page 499
5.5.2.3 Thermal noise......Page 500
5.5.2.4 Flicker noise......Page 501
5.5.2.5 Offset voltage due to local-area mismatch......Page 502
5.5.2.6 Input and output capacitances......Page 504
5.5.2.8 Input and output voltage ranges......Page 505
5.5.2.10 Layout area......Page 506
5.5.2.11 Tradeoffs in DC accuracy, low-frequency AC accuracy, voltage gain, and transconductance bandwidth......Page 508
5.5.3 Other Optimizations: Ensuring Input Devices Dominate Flicker Noise and Local-Area Mismatch......Page 510
5.5.4 Other Optimizations: Complementing the Design......Page 511
5.6 Prediction Accuracy for Design Guidance and Optimization......Page 512
References......Page 514
6.1 Introduction......Page 515
6.2 Using the Lateral Bipolar Transistor for Low-Flicker-Noise Applications......Page 516
6.3.1 Thermal-Noise Efficiency Factor......Page 517
6.3.2 Flicker-Noise Area Efficiency Factor......Page 520
6.4 Reported Micropower, Low-Noise CMOS Preamplifiers......Page 521
6.5.1 Transconductance in Saturation......Page 524
6.5.2 Drain–Source Resistance and Transconductance in the Deep Ohmic Region......Page 527
6.5.3.1 Thermal noise......Page 529
6.5.3.2 Flicker noise......Page 531
6.5.4.2 Flicker noise......Page 532
6.5.5.1 Bias compliance voltage......Page 534
6.5.5.2 Thermal noise......Page 535
6.5.5.3 Flicker noise......Page 538
6.6.1 Preamplifier Input Devices......Page 542
6.6.2 Preamplifier Non-Input Devices......Page 544
6.7.1 Description......Page 545
6.7.2 Circuit Analysis, Performance Optimization, and Predicted Performance......Page 547
6.7.2.1 Voltage gain......Page 548
6.7.2.3 Thermal noise......Page 549
6.7.2.4 Thermal noise expressed from DC bias conditions......Page 550
6.7.2.5 Flicker noise......Page 554
6.7.2.6 Flicker noise expressed from DC bias conditions......Page 555
6.7.3 Summary of Predicted and Measured Performance......Page 558
6.7.3.1 MOSFET design selections......Page 559
6.7.3.2 Resulting preamplifier performance......Page 563
6.7.4 Design Improvements......Page 567
6.8.1 Description......Page 569
6.8.2 Circuit Analysis, Performance Optimization, and Predicted Performance......Page 570
6.8.2.1 Voltage gain......Page 571
6.8.2.2 Frequency response......Page 572
6.8.2.3 Thermal noise......Page 573
6.8.2.4 Thermal noise expressed from DC bias conditions......Page 574
6.8.2.5 Flicker noise......Page 576
6.8.2.6 Flicker noise expressed from DC bias conditions......Page 577
6.8.3.1 MOSFET design selections......Page 579
6.8.3.2 Resulting preamplifier performance......Page 581
6.8.4 Design Improvements......Page 585
6.9 Prediction Accuracy for Design Guidance and Optimization......Page 587
6.10 Summary of Low-Noise Design Methods and Resulting Challenges in Low-Voltage Processes......Page 588
References......Page 590
7.1 Introduction......Page 593
7.2.2 Other Nearly Universal Performance Characteristics Across CMOS Processes......Page 594
7.2.3 Porting Designs Across CMOS Processes......Page 595
7.3 Enhancing Optimization Methods by Including Gate Leakage Current Effects......Page 598
7.4 Using an Inversion Coefficient Measure for Non-CMOS Technologies......Page 599
References......Page 600
Appendix: The Analog CMOS Design, Tradeoffs and Optimization Spreadsheet......Page 603
Index......Page 621
