Author(s): David Patterson; Andrew Waterman
Edition: Beta edition, 0.0.1
Publisher: Strawberry Canyon LLC
Year: 2017
Language: English
Pages: 192
City: Berkeley, California
Tags: Computer architecture, RISC microprocessors, Assembly languages (Electronic computers)
List of Figures
Preface
Why RISC-V?
Introduction
Modular vs. Incremental ISAs
ISA Design 101
An Overview of this Book
Concluding Remarks
To Learn More
RV32I: RISC-V Base Integer ISA
Introduction
RV32I Instruction formats
RV32I Registers
RV32I Integer Computation
RV32I Loads and Stores
RV32I Conditional Branch
RV32I Unconditional Jump
RV32I Miscellaneous
Comparing RV32I, ARM-32, MIPS-32, and x86-32
Concluding Remarks
To Learn More
RISC-V Assembly Language
Introduction
Calling convention
Assembly
Linker
Static vs. Dynamic Linking
Loader
Concluding Remarks
To Learn More
RV32M: Multiply and Divide
Introduction
Concluding Remarks
To Learn More
RV32FD: Single/Double Floating Point
Introduction
Floating-Point Registers
Floating-Point Loads, Stores, and Arithmetic
Floating-Point Moves and Converts
Miscellaneous Floating-Point Instructions
Comparing RV32FD, ARM-32, MIPS-32, and x86-32 using DAXPY
Concluding Remarks
To Learn More
RV32A: Atomic
Introduction
Concluding Remarks
To Learn More
RV32C: Compressed Instructions
Introduction
Comparing RV32GC, Thumb-2, microMIPS, and x86-32
Concluding Remarks
To Learn More
RV32V: Vector
Introduction
Vector Computation Instructions
Vector Registers and Dynamic Typing
Vector Loads and Stores
Parallelism During Vector Execution
Conditional Execution of Vector Operations
Miscellaneous Vector Instructions
Vector Example: DAXPY in RV32V
Comparing RV32V, MIPS-32 MSA SIMD, and x86-32 AVX SIMD
Concluding Remarks
To Learn More
RV64: 64-bit Address Instructions
Introduction
Comparison to Other 64-bit ISAs using Insertion Sort
Program size
Concluding Remarks
To Learn More
RV32/64 Privileged Architecture
Introduction
Machine Mode for Simple Embedded Systems
Machine-Mode Exception Handling
User Mode and Process Isolation in Embedded Systems
Supervisor Mode for Modern Operating Systems
Page-Based Virtual Memory
Concluding Remarks
To Learn More
Future RISC-V Optional Extensions
``B'' Standard Extension for Bit Manipulation
``E'' Standard Extension for Embedded
``H'' Privileged Architecture Extension for Hypervisor Support
``J'' Standard Extension for Dynamically Translated Languages
``L'' Standard Extension for Decimal Floating-Point
``N'' Standard Extension for User-Level Interrupts
``P'' Standard Extension for Packed-SIMD Instructions
``Q'' Standard Extension for Quad-Precision Floating-Point
Concluding Remarks
RISC-V Instruction Listings
Index
