The Fourth Terminal: Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems

Foreword
Acknowledgements
Contents
Acronyms
1 Introduction
1.1 Foreword
1.2 Analog Design Aspects
1.3 Digital Design Aspects
1.4 Book Overview
References
Part I Device Level and General Studies for Analog and Digital
2 FD-SOI Technology
2.1 Introduction
2.2 FD-SOI Technology Description and Basic Equations
2.3 Transistor Parameters and Body-Bias
2.4 Transistor Variability
2.5 Digital Performance Enhancement with FBB
2.6 Analog Performance Enhancement with FBB
2.7 SRAM Bit-Cell
2.8 Body-Bias Impact on Device Reliability
2.8.1 Case of Gate Oxide Breakdown
2.8.2 Case of NBTI
2.8.3 Case of HCI
2.9 Conclusion
References
3 Body-Bias for Digital Designs
3.1 Body-Bias for Digital Designs: Introduction
3.1.1 Body-Bias and the Digital Design Space
3.1.2 Logic Performance Benchmark Method
3.2 Digital Compensation Toolbox
3.2.1 Temperature Compensation
3.2.2 Voltage Compensation or Body-Bias Modulation with Voltage
3.2.3 Process Compensation
3.2.4 Ageing Compensation
3.2.5 Asymmetric Body-Bias
3.2.6 Compensation Costs and Gains
3.2.6.1 Body-Bias Leakage Reduction
3.2.6.2 Body-Bias Dynamic Power Gains
3.2.6.3 Yield or Minimum Operational Voltage Gain
3.2.6.4 Body-Bias Engineering and Deployment Costs
3.2.7 Open Loop Bias Law
3.3 Body-Bias Design Limits
3.3.1 The Design Leakage Ceiling
3.3.2 Thermal Bound
3.3.3 The Unbiased Parts Timing Ceiling
3.3.4 Biasing the Other Way
3.4 Digital Performance Boost
3.5 Ultra-Low Voltage Designs
3.6 Body-Bias for Digital Designs: Conclusion
References
4 Body-Biasing in FD-SOI for Analog, RF, and Millimeter-Wave Designs
4.1 Introduction
4.2 On the Usage of Variable Body-Biasing Voltage on Chip
4.3 On the Usage of Fixed Body-Bias Voltage on Chip
References
5 SRAM Bitcell Functionality Under Body-Bias
5.1 Silicon Product Yield in a Highly Competitive Market
5.2 The SRAM Expand-and-Shrink Trend
5.3 Should We Measure or Calculate the SRAM Yield?
5.4 The SRAM Circuit
5.5 Can SRAM Spice Models Predict Yield?
5.6 Supported Operating Voltage Range: The Vmin Paradigm
5.7 From Margins to Failure Rate: Validity of a LF Gaussian Model Across Temperatures
5.8 Body-Bias Effects to SRAM
5.9 Understanding HF Effects
5.10 Switching to the Nmax Paradigm to Support Body-Bias
5.11 HF Body-Bias Effects and Future SRAM Compensation Applications
5.12 Conclusions
References
Part II Design Examples: From Analog RF and mmW to Digital. From Building Blocks and Circuits to SoCs
6 Coarse/Fine Delay Element Design in 28nm FD-SOI
6.1 Delay Elements Review
6.1.1 Cascaded Inverters
6.1.2 Capacitive Shunting
6.1.3 The Semi-static Approach
6.1.4 Current Starving
6.1.5 Thyristor Delay Elements
6.1.6 Choosing a Delay Element
6.2 Coarse/Fine-Tuning Delay Element and Line Using Gate and Body-Biasing in 28nm FD-SOI
6.2.1 Delay Element Design
6.2.2 Delay Line Architecture
6.2.3 Delay Line Measurement Results
References
7 Millimeter-Wave Distributed Oscillators in 28nm FD-SOI Technology
7.1 Introduction
7.2 Distributed Oscillator Theory for Operation Frequencies Close to fmax
7.3 Amplification Stage Design
7.4 Transmission Line Design
7.5 Circuits Measurements
7.5.1 Standalone Transistor Measurements
7.5.2 Measurement Setup
7.5.3 Measurement Results
7.5.4 On-Wafer Mapping Measurement for Variability Study
7.5.5 Phase Noise Optimization Through Body-Bias Control
7.6 State-of-the-Art Comparison and Conclusion
References
8 Millimeter-Wave Power Amplifiers for 5G Applications in 28nm FD-SOI Technology
8.1 Introduction
8.1.1 Design Flow for Integrated mmW PA Design
8.1.2 Power Amplifier Configurability Discussion in the Context of FD-SOI Technologies
8.2 Reconfigurable Balanced mmW PA Implementation in 28nm FD-SOI Technology
8.2.1 Active Devices
8.2.1.1 Dimensioning
8.2.1.2 Layout Optimization Strategy
8.2.2 Power Amplifier Topology
8.2.2.1 Choice of Overall Topology
8.2.2.2 Balanced Topology Implementation
8.2.3 Power Stages Design
8.2.3.1 Design and Implementation of S2 Power Amplification Stage
8.2.3.2 Design and Implementation of S1 Power Amplification Stage
8.2.4 Impedance Matching Network Implementation
8.2.4.1 Output Matching Network Optimization Strategy
8.2.4.2 Inter-Stage and Input Matching
8.2.5 Robust Integration and Reliability
8.2.5.1 ESD Protection
8.2.5.2 Electromigration
8.2.5.3 Safe Operating Area
8.2.5.4 Ground Return Path Optimization
8.3 mmW Power Amplifier Measurement Results
8.3.1 Measurements at Optimal Operating Point
8.3.2 Small-Signal Measurements with Body-Biasing Tuning
8.3.3 Large-Signal Measurements with Body-Biasing Tuning
8.3.4 AM–PM Measurements with Body-Biasing Tuning
8.3.5 Measurements Over Frequency Range
8.3.6 Power Amplifier Behavior for Temperature Variations
8.3.6.1 Large-Signal Measurements from 25 to 125C with Body-Biasing Tuning
8.3.6.2 Small-Signal Measurements from 25 to 125C
8.3.7 On-Wafer Variability Statistical Study
8.4 Comparison and Discussion Regarding mmW PA State of the Art
References
9 An 802.15.4 IR-UWB Transmitter SoC with Adaptive-FBB-Based Channel Selection andProgrammable Pulse Shape
9.1 Introduction
9.2 Architecture of the Digital TX
9.3 Duty-Cycled Frequency Synthesis
9.4 Pulse-Shaping Digital Power Amplifier
9.5 FBB Generation and Current-Matching Loop
9.6 SoC Integration
9.7 Measurement Results
9.8 Conclusions
References
10 Body-Bias Calibration Based Temperature Sensor
10.1 Introduction
10.1.1 Temperature Sensor Requirements for Modern SoCs
10.1.1.1 Need for Temperature Monitoring of Digital SoCs
10.1.1.2 Integrated Temperature Sensor Requirements
10.1.2 Current Methods for Temperature Sensors Design and Process Compensation
10.1.2.1 Analog Bandgap
10.1.2.2 Resistor-Based
10.1.2.3 Thermal Diffusivity
10.1.2.4 Digital Differential CMOS
10.1.2.5 Single-Ended Digital Temperature Sensor (SED-THS)
10.2 Body-Bias Compensated Oscillator Principle
10.2.1 Uncompensated SED-THS
10.2.1.1 Basic Principle
10.2.1.2 Simulated Performance
10.2.2 Bias-Compensated SED-THS
10.2.2.1 Use of Body-Bias Compensation
10.2.2.2 Supply-Bias Merged Oscillator
10.2.2.3 Oscillator Performance
10.3 Circuit Implementation
10.3.1 Probe Detailed Implementation
10.3.2 Digital Processing
10.3.3 Noise Analysis Methodology
10.4 Manufactured Chip
10.4.1 Sensor Layout
10.4.2 Validation of Calibration
10.4.2.1 Measured Accuracy
10.4.2.2 Example of SoC Integration
10.4.2.3 State-of-the-Art Summary
10.5 Conclusion
References
11 System Integration of RISC-V Processors with FD-SOI
11.1 SoC Design in FD-SOI
11.1.1 Raven-3
11.1.2 Raven-4
11.2 RISC-V Processors
11.2.1 Rocket Chip
11.2.2 Hwacha Vector Processor
11.2.3 Z-Scale
11.3 Energy-Efficient SRAMs
11.4 DC-DC Converters
11.5 Body-Bias Generation
11.6 Clock Generation
11.6.1 DLL-Based Adaptive Clocking
11.6.2 Free-Running Adaptive Clocking
11.7 System Performance
11.7.1 Raven-3 Measurement Results
11.7.2 Raven-4 Measurement Results
References
Part III Body-Bias Deployment in Mixed-Signal and Digital SoCs
12 Timing-Based Closed Loop Compensation
12.1 Closed-Loop Timing Monitoring
12.1.1 Introduction
12.2 Speed Monitors
12.2.1 Ring Oscillator Based Monitors
12.2.2 Tunable Replica Circuits
12.2.2.1 Multi-Cell Type Path Composition
12.2.2.2 Single-Cell Type Path Composition
12.2.3 Endpoint Monitors
12.2.4 Critical Path Replica
12.2.5 Monitor Calibration
12.2.5.1 Timing Margin Elaboration
12.2.6 Monitor Evaluation
12.2.6.1 Ring Oscillator Based Monitors
12.2.6.2 Tunable Replica Circuits
12.2.6.3 Endpoint Monitors
12.2.6.4 Critical Path Replicas
12.3 Control Functions
12.3.1 Successive Approximation
12.3.2 Proportional Control
12.3.3 Proportional-Integral Control
12.3.4 Proportional-Derivative Control
12.4 Design Example: Process and Temperature Timing-Based Closed Loop Compensation
12.4.1 Architecture
12.4.2 Compensation Unit
12.4.3 Speed Monitor
12.4.4 Measurements
References
13 Open Loop Compensation
13.1 Circuits Content
13.2 Mixed ASIC Flow and Software Based Open Loop Body-Bias Controller
13.3 Full ASIC Flow Based Open Loop Body-Bias Controller
13.4 Open Loop Controller Solution Design Synthesis
References
14 Compensation and Regulation Solutions' Synthesis
14.1 Body-Bias and Voltage Scaling
14.1.1 Introduction
14.1.2 Comparison
14.1.2.1 Variation Compensation
14.1.2.2 Process Compensation
14.1.2.3 Voltage Compensation
14.1.2.4 Temperature Compensation
14.1.2.5 Ageing
14.1.2.6 Speed Boost
14.1.2.7 Selective N vs P Adjustment
14.1.2.8 Multiple Domain Adjustment
14.1.3 Combination of the Two
14.2 Body-Bias Control: Closed-Loop vs Open-Loop
References
15 Body-Bias Voltage Generation
15.1 Introduction
15.2 Load Model Description and Modelling
15.2.1 Common Load Topology
15.2.2 Currents
15.2.3 Capacitances
15.2.4 Load Estimation
15.3 Specifications and Constraints for a Body-Bias Voltage Generator
15.3.1 Timing
15.3.2 Voltage Range
15.3.3 Environmental Constraints
15.4 Body-Bias Voltage Generator Design
15.4.1 Voltage Reference
15.4.2 Programmable Voltage Generation
15.4.3 Output Stages
15.4.3.1 Analogue Output Buffer
15.4.3.2 Digital Output Buffer
15.4.3.3 Negative Voltage Generation
15.4.3.4 Loop Regulation for Clocked Power Stages
15.4.4 BBGEN Architecture Examples
15.5 Body-Bias Voltage Generator Implementation at System on Chip Level
15.5.1 Power Integrity Concern
15.5.2 Placement Concern
15.5.3 Testability
15.6 Conclusion
References
16 Digital Design Implementation Flow and VerificationMethodology
Digital Flow Steps and Vocabulary
16.1 Specification and Engineering Test Body-Bias Prerequisites
16.2 Design Startup Caution
16.3 Design Verification Principles and Corners Definition
16.3.1 Design Verification Principles
16.3.2 Design Corners Definition
16.3.2.1 Which Corner for Setup Timing Check, for Hold Timing Check?
16.3.2.2 Design Verification Corners Definition Step by Step Method
16.3.2.3 Verification Corners Versus Implementation Corners
16.4 Physical Implementation
16.4.1 Implementation Timing Corner Selection
16.4.2 Specific Addition to Standard Flow
16.4.3 Low-Power Flow
A FD-SOI Process Flow
B Digital Implementation Flow and Terminology
B.1 Digital Design Wording and Body-Bias
B.1.1 Quality of Results
B.1.2 Corner, Mode and Scenario
B.1.3 Temperature Inversion, VTinv and ZTC
B.1.4 Implementation and Sign-Off
B.1.5 Functional Simulation and Static Timing Analysis
B.1.6 Clock Tree and Clock Skew
B.1.7 High Fanout Nets
B.1.8 Convergence and Correlation
B.1.9 Sequential Design, the Digital Sheep Shepherd Problem
B.2 Digital Design Rules and Constraints Definition
B.2.1 Setup Constraint
B.2.2 Hold Constraint
B.2.3 Clock Minimum Pulse Width Constraint
B.2.4 Maximum Fanout Load Capacitance, Signal Transition Rules
B.3 Flow Steps
B.3.1 Front-End
B.3.1.1 Synthesis
B.3.1.2 DFT Insertion
B.3.1.3 Formal Proof
B.3.2 Back-End
B.3.2.1 Floorplan
B.3.2.2 Placement
B.3.2.3 Clock Tree Synthesis
B.3.2.4 Routing
B.3.2.5 Finishing
B.3.3 Sign-Off
B.3.3.1 Extraction
B.3.3.2 Static Timing Analysis
B.3.3.3 Power and Voltage Drop Analysis
B.3.3.4 Design Rule Check and Layout Versus Schematic
C IEEE 1801 UPF Example
References
Index