System-Level Modeling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures

Contents......Page 8
Acknowledgments......Page 6
1 Introduction......Page 10
1.1 Related work in system-level design......Page 14
1.2 Organization and contributions of this thesis......Page 17
2 The Sesame environment......Page 20
2.1 Trace-driven co-simulation......Page 22
2.2 Application layer......Page 23
2.3 Architecture layer......Page 26
2.4 Mapping layer......Page 29
2.5 Implementation aspects......Page 31
2.5.1 Application simulator......Page 35
2.5.2 Architecture simulator......Page 37
2.6 Mapping decision support......Page 39
2.7 Obtaining numbers for system-level simulation......Page 40
2.8 Summary......Page 42
3 Multiobjective application mapping......Page 44
3.1 Related work on pruning and exploration......Page 46
3.2.1 Application modeling......Page 48
3.2.2 Architecture modeling......Page 49
3.2.3 The mapping problem......Page 50
3.3.1 Preliminaries......Page 52
3.3.3 Multiobjective evolutionary algorithms (MOEAs)......Page 55
3.3.4 Metrics for comparing nondominated sets......Page 60
3.4 Experiments......Page 62
3.4.1 MOEA performance comparisons......Page 65
3.4.2 Effect of crossover and mutation......Page 70
3.5 Conclusion......Page 73
4 Dataflow-based trace transformations......Page 76
4.1 Traces and trace transformations......Page 78
4.2 The new mapping strategy......Page 83
4.3 Dataflow actors in Sesame......Page 86
4.3.2 SDF actors for architecture events......Page 87
4.3.3 Token exchange mechanism in Sesame......Page 89
4.3.4 IDF actors for conditional code and loops......Page 90
4.4 Dataflow actors for event refinement......Page 92
4.5 Trace refinement experiment......Page 95
4.6 Conclusion......Page 99
5 Motion-JPEG encoder case studies......Page 102
5.1 Sesame: Pruning, exploration, and refinement......Page 103
5.2 Artemis: Calibration and validation......Page 110
5.3 Conclusion......Page 114
6 Real-time issues......Page 116
6.1 Problem definition......Page 117
6.2 Recurring real-time task model......Page 119
6.2.1 Demand bound and request bound functions......Page 120
6.2.2 Computing request bound function......Page 122
6.3 Schedulability under static priority scheduling......Page 123
6.4 Dynamic priority scheduling......Page 126
6.5 Simulated annealing framework......Page 127
6.6 Experimental results......Page 129
6.7 Conclusion......Page 132
7 Conclusion......Page 134
A Performance metrics......Page 136
B Task systems......Page 140
References......Page 144
Nederlandse samenvatting......Page 150
Scientific output......Page 152
Biography......Page 154