Switch/Router Architectures: Systems with Crossbar Switch Fabrics

Cover
Half Title
Title
Copyright
Contents
Preface
Author
Part
1 Characteristics of Switch/Routers with Crossbar Switch Fabrics
Chapter 1 The Switch/Router: Integrated OSI Layers 2 and 3 Forwarding on a Single Platform
1.1 Introduction
1.2 Flow-Based Layer 3 Forwarding
1.3 Network Topology-Based Layer 3 Forwarding
1.4 Using Centralized or Distributed Forwarding Engines
1.4.1 Forwarding Using a Centralized Forwarding Engine
1.4.2 Forwarding Using Distributed Forwarding Engines
1.5 Building the Layer 2 Forwarding Tables
1.5.1 MAC Address Aging
1.5.2 Synchronizing MAC Address Tables in a Distributed Forwarding Architecture
1.5.3 History of MAC Address Changes
1.6 Memory Architectures for Storing Forwarding Databases
1.6.1 Content Addressable Memory (CAM)
1.6.2 Ternary Content Addressable Memory (TCAM)
1.7 Physical and Logical Interfaces on a Switch/Router
1.7.1 Layer 2 (Switch) Interfaces
1.7.1.1 Access Ports
1.7.1.2 Access Ports and Tagged Packets
1.7.1.3 Trunk Ports
1.7.1.4 Port Channels or Port Groups
1.7.2 Layer 3 (Routed) Interfaces
1.7.2.1 Physical Layer 3 (Routed) Interfaces
1.7.2.2 Logical Layer 3 (Routed) Interfaces (VLAN Interfaces or Switch Virtual Interfaces (SVIs))
1.7.3 Subinterfaces
1.7.4 Loopback Interfaces
1.7.4.1 Local Communications
1.7.4.2 Testing and Performance Analysis
1.7.4.3 Device Identification
1.7.4.4 Routing Information Maintenance
1.7.5 Tunnel Interfaces
1.7.5.1 Layer 3 Tunnel Interfaces/Ports Examples
1.7.5.2 Layer 2 Tunnel Interfaces/Ports Examples
1.7.6 Port Channels
1.7.6.1 Layer 2 and Layer 3 Port Channels
1.7.6.2 Load Balancing
1.7.6.3 Dynamic Configuration of Port Channels
1.8 Challenges
References
Chapter 2 Understanding Crossbar Switch Fabrics
2.1 Introduction
2.2 The Crossbar Switch Fabric
2.2.1 Implementing a Crossbar Switch
2.2.2 Building Multistage Switches
2.2.3 Challenges in Building Larger Crosspoint Arrays
2.2.4 Designing Today’s System Interconnects
2.3 Logical Architecture and Improving Data Transfer Throughput
2.4 Components of a Practical Crossbar Switch Fabric System
2.5 Traffic Scheduling in the Crossbar Switch
2.5.1 The Scheduling Problem
2.5.2 Parallel Iterative Matching (PIM)
2.5.3 Round-Robin Matching (RRM)
2.5.4 Iterative Round-Robin Matching with Slip (iSLIP)
2.5.5 Other Considerations in the Design of Schedulers
2.6 Handling Multicast Traffic
2.6.1 Multicast Packet Replication
2.6.2 Multicast Traffic Scheduling
2.6.2.1 Full versus Partial Multicast Scheduling across the Crossbar Switch Fabric
2.6.2.2 Scheduling in Internally Unbuffered Crossbar Switches
2.6.2.3 Scheduling in Internally Buffered Crossbar Switches
2.6.2.4 Special Focus: The ESLIP Scheduling Algorithm
2.7 Data Transfer Process over the Switch Fabric
2.8 System Monitoring and Control
2.8.1 Main MBus Functions
2.8.2 Alarm Functionality
2.9 Scalability
2.10 Fault Tolerance
2.11 Generic Switch/Router with Crossbar Switch Fabric
References
Chapter 3 Introduction to Switch/Routers with Crossbar Switch Fabrics
3.1 The Crossbar Switch Fabric
3.2 Architectures with Crossbar-Based Switch Fabrics and Centralized Forwarding Engines
3.2.1 Architectures with Forwarding Using a Flow/Route Cache in Centralized Processor
3.2.2 Architectures with Forwarding Using an Optimized Lookup System in Centralized Processor
3.3 Architectures with Crossbar-Based Switch Fabrics and Distributed Forwarding Engines
3.3.1 Architectures with Forwarding Engine and Flow/Route Cache in Line Cards
3.3.2 Architectures with Fully Distributed Forwarding Engines in Line Cards
3.4 Relating Architectures to Switch/Router Types
Part
2 Design Examples and Case Studies
Chapter 4 Cisco Catalyst 6500 Series Switches with Supervisor Engines 1A and 2
4.1 Introduction
4.2 Main Architectural Features of the Catalyst 6500 Series
4.3 Catalyst 6500 Switch Fabric Architecture
4.4 Catalyst 6500 Line Cards Architectures
4.4.1 Fabric-Enabled Line Cards
4.4.2 Fabric-Only Line Cards
4.5 Catalyst 6500 Control Plane Implementation and Forwarding Engines—Supervisor Engines
4.5.1 Supervisor Engine 1A Architecture
4.5.1.1 Supervisor Engine 1A with Only a PFC1
4.5.1.2 Supervisor Engine 1A with a PFC1 and MSFC1/MSFC2
4.5.2 Supervisor Engine 2 Architecture
4.5.2.1 Supervisor Engine 2 with a PFC2
4.5.2.2 Supervisor Engine 2 with a PFC2 and MSFC2
4.5.3 Supporting High Availability with Dual Supervisor Engines
4.5.4 Distributed Forwarding Card
4.5.4.1 Packet Forwarding in the DFC
4.6 Packet Flow in the Catalyst 6500
4.6.1 Packet Flow in the Catalyst 6500 with Centralized Forwarding
4.6.2 Packet Flow in the Catalyst 6500 with Distributed Forwarding
References
Chapter 5 Avaya P580 and P882 Routing Switch Architecture with 80-Series Media Module
5.1 Introduction
5.2 Basic Architecture
5.3 Data Flow through the Avaya 80-Series Switch
5.4 Quality of Service (QoS) Mechanisms
5.4.1 Classification Precedence
5.4.2 DiffServ Mapping Table
5.4.3 Queuing and Scheduling
5.4.4 Traffic Management
5.4.5 IEEE 802.1p/Q and DSCP or ToS Standards in the Avaya 80-Series
5.4.5.1 DiffServ’s Per-Hop Behaviors (PHB)
5.4.5.2 Packet Loss Priority (PLP)
5.4.5.3 Avaya 80-Series Recommendations for IEEE 802.1p/Q, DSCP Code Point, and Queues
5.5 Designing the High-Performance Switch/Router
References
Chapter 6 Foundry Networks Multilayer Switches with IronCoreTM Network Interface Module
6.1 Introduction
6.2 Switch Chassis Overview
6.3 Chassis Crossbar Switch Fabric
6.4 IronCoreTM Network Interface Module Architecture
6.4.1 Network Interface Module Components
6.4.1.1 Physical Ports
6.4.1.2 Multi-Port MAC
6.4.2 Packet Processor—The Forwarding Engine of IronCore
6.4.3 Route Processor Components
6.4.3.1 System Management Module/Board—The Route Processor Module
6.4.3.2 System Management Interface/CPU
6.4.3.3 CPU Path and Data Transfer Engine Path
6.4.3.4 Management Bus
6.4.4 Shared Memory and Switch Fabric Interface Components
6.4.4.1 Shared-Memory Switch Fabric and Buffer Pool
6.4.4.2 Data Transfer Engine
6.4.4.3 Crossbar Backplane Connection—Module Connection to Crossbar Switch Fabric
6.4.4.4 Multiple Destination Output Priority Queues
6.4.4.5 Multiple Input Source Buffers per Output Port
6.5 BigIron 4000 Complete Crossbar Switch System
6.6 Packet Processing Overview
6.6.1 Role of the Data Transfer Engine and Packet Flow for Unicast and Multicast Traffic
6.6.1.1 Forwarding Unicast Traffic
6.6.1.2 Forwarding Multicast Traffic
6.7 Important Attributes of the Shared-Memory Based IronCore Architecture
References
Chapter 7 Foundry Networks Multilayer Switches with JetCoreTM Network Interface Module
7.1 Introduction
7.2 JetCoreTM Network Interface Module Architecture
7.2.1 Network Interface Components
7.2.1.1 Physical Ports
7.2.1.2 Media Access Controller (MAC)
7.2.2 JetCore Forwarding Engine Components
7.2.2.1 Packet Classifier—The Forwarding Engine of JetCore
7.2.2.2 Content Addressable Memory (CAM)
7.2.2.3 Parameter Random Access Memory (PRAM)
7.2.2.4 VLAN Multicast Assist Module
7.2.2.5 Transmit Pipeline
7.2.3 Memory Components of the Port Group Switching Logic and Switch Fabric
7.2.3.1 Shared-Memory Switch Fabric
7.2.3.2 Buffer Manager
7.2.3.3 Shared-Memory Buffer Pool
7.2.4 Route Processor Components
7.2.4.1 Command Bus
7.2.4.2 System Management Interface
7.2.5 Module Crossbar Switch Fabric
7.2.5.1 Backplane Connectivity
7.2.5.2 Replication of Multicast Packets
7.2.6 Multiple Destination Output Priority Queues
7.3 Other JetCore Features
7.4 Packet Processing Overview
7.4.1 Packet Flow for Unicast and Multicast Traffic
7.4.1.1 Forwarding Unicast Traffic to Destination Port(s) on a Different Module Crossbar Switch Fabric
7.4.1.2 Forwarding Multicast Traffic to Destination Port(s) on Different Module Crossbar Switch Fabric(s)
7.5 Foundry IronWareTM Software Architecture
7.6 Switching and Routing Architecture
7.6.1 Foundry Switching and Routing Architecture
7.6.2 Packet Handling Mechanisms in the Multilayer Switch
7.6.3 FastIron Multilayer Switch Architecture
7.6.4 BigIron, NetIron, and TurboIron Multilayer Switch Architecture
Reference
Chapter 8 Cisco Catalyst 6500 Series Switches with Supervisor Engine 720
8.1 Introduction
8.2 Cisco Catalyst 6500 Backplane
8.3 Cisco Catalyst 6500 Crossbar Switch Fabric
8.4 Supervisor Engine 720
8.4.1 Multilayer Switch Feature Card 3 (MSFC3)
8.4.2 Policy Feature Card 3 (PFC3)
8.5 Supervisor Engine 720–3B
8.5.1 Policy Feature Card 3B (PFC3B)
8.6 Supervisor Engine 720–3BXL
8.6.1 Policy Feature Card 3BXL (PFC3BXL)
8.7 Packet Forwarding in Supervisor Engines 720, 720–3B, and 720–3BXL
8.8 Catalyst 6500 Line Cards Supported by Supervisor Engine 720
8.8.1 dCEF256 Line Card Architecture
8.8.2 CEF720 Line Card Architecture
8.8.3 dCEF720 Line Card Architecture
8.9 Functional Elements of Distributed Forwarding Card (DFC) and Policy Feature Card (PFC)
8.9.1 A Note on NetFlow
8.9.2 Access Control Lists for QoS and Security Processing
8.9.3 Distributed Forwarding Operations in Catalyst 6500 with PFC or DFC
8.10 Packet Flow in the Catalyst 6500 with Supervisor Engine 720
8.10.1 Centralized Forwarding
8.10.2 Distributed Forwarding
8.10.3 Flow Cache-Based Packet Forwarding—Accelerated Cisco Express Forwarding (aCEF)
References
Chapter 9 Multicast Routing and Multicast Forwarding Information Base (MFIB) Architecture
9.1 Introduction
9.2 Benefits of the MFIB Architecture
9.3 Protocol-Independent Multicast (PIM)
9.4 Types of Multicast Table Entries
9.4.1 Multicast Table Context
9.5 Types of Multicast Tables
9.5.1 IGMP Cache
9.5.2 Reverse-Path Forwarding (RPF) Table
9.5.3 PIM Dense Mode (PIM-DM) Table Entries
9.5.4 PIM Sparse Mode (PIM-SM) Table Entries
9.5.4.1 Concept of Rendezvous Point
9.5.4.2 PIM-SM Router Architecture
9.5.4.3 Sending Multicast Data
9.5.4.4 Receiving Multicast Data
9.5.4.5 PIM Assert Mechanism
9.5.4.6 Electing the PIM Forwarder—PIM Assert Winner
9.5.5 PIM Sparse-Dense Mode
9.5.5.1 Auto-RP
9.5.5.2 Using PIM Sparse-Dense with Auto-RP
9.5.6 Multicast Source Discovery Protocol (MSDP) Cache
9.5.6.1 MSDP Peer-RPF Checks
9.5.7 PIM Source Specific Multicast (PIM-SSM) Table Entries
9.5.8 Bidirectional PIM (BIDIR-PIM) Table Entries
9.5.8.1 Designated Forwarder Election
9.5.8.2 Building the Bidirectional Group Tree and Packet Forwarding
9.6 Multicast Reverse Path Forwarding (RPF)
9.6.1 Using the RPF Table
9.6.2 Data-Plane versus Control-Plane RPF Check
9.6.3 RPF Check
9.7 MFIB Components
9.7.1 Protocols and Tables Used in IP Multicast Routing
9.7.2 Layers 2 and 3 Multicast Tables Entries in a Switch/Router
9.7.2.1 Benefits of IGMP Snooping
9.7.3 Multicast Fast Drop
9.7.4 Using the Multicast Routing Information Base (MRIB)
9.7.5 Using the Multicast Forwarding Information Base (MFIB)
9.7.6 Using the Distributed MFIB
9.8 Multicast Packet Forwarding Using the MFIB
9.8.1 Process Switching
9.8.2 Fast-Path Processing Using Flow/Route Caching
9.8.3 Fast-Path Processing Using Optimized Forwarding Table Lookup Structures (without Flow/Route Caching)
9.9 PIM-SM Tunnel Interfaces
References
Chapter 10 Unicast versus Multicast Packet Forwarding: A Case Study
10.1 Introduction
10.2 Unicast Forwarding Table and TCAM Lookup Architecture
10.3 Unicast Forwarding Examples
10.3.1 Catalyst 6500 Supervisor Engine 2
10.3.2 Supervisor Engine 32
10.3.3 Catalyst 6500 Supervisor Engine 720
10.4 Multicast Forwarding Tables and TCAM Lookup Architecture
10.5 Multicast Packet Replication
10.5.1 Centralized Packet Replication
10.5.2 Packet Replication in the Line Cards
10.5.2.1 Ingress Multicast Packet Replication
10.5.2.2 Egress Multicast Packet Replication
10.5.3 Combined Replication Methods
10.5.4 Packet Replication at Layer 3 versus Layer 2
10.5.5 Packet Replication in the Switch Fabric: Preferred Method
10.6 Multicast Forwarding Architecture Example: Catalyst 6500 Supervisor Engine 720
10.6.1 Ingress Packet Replication Mode Example: Catalyst 6500 Supervisor Engine 720
10.6.2 Egress Packet Replication Mode Example: Catalyst 6500 Supervisor Engine 720
References
Index