Software and Compilers for Embedded Systems: 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003. Proceedings

This document was uploaded by one of our users. The uploader already confirmed that they had the permission to publish it. If you are author/publisher or own the copyright of this documents, please report to us by using this DMCA report form.

Simply click on the Download Book button.

Yes, Book downloads on Ebookily are 100% Free.

Sometimes the book is free on Amazon As well, so go ahead and hit "Search on Amazon"

This volume contains the proceedings of the 7th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2003, held in Vienna, Austria, September 24–26, 2003. Initially, the workshop was referred to as the International Workshop on Code Generation for Embedded Systems. The ?rst workshop took place in 1994 in Schloss Dagstuhl, Germany. From its beg- nings, the intention of the organizers was to create an atmosphere in which the researcherscould participateactively in dynamic discussionsand pro?t from the assembly of international experts in the ?eld. It was at the fourth workshop, in St. Goar, Germany, in 1999, that the spectrum of topics of interest for the workshop was extended, and not only code generation, but also software and compilers for embedded systems, were considered. The change in ?elds of interest led to a change of name, and this is when the present name was used for the ?rst time. Since then, SCOPES has been held again in St. Goar, Germany, in 2001; Berlin, Germany, in 2002; and this year, 2003, in Vienna, Austria. In response to the call for papers, 43 very strong papers from all over the world were submitted. The program committee selected 26 papers for pres- tation at SCOPES 2003. All submitted papers were reviewed by at least three experts in order to ensure the quality of the work presented at the workshop.

Author(s): James C. Dehnert (auth.), Andreas Krall (eds.)
Series: Lecture Notes in Computer Science 2826
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2003

Language: English
Pages: 406
Tags: Programming Languages, Compilers, Interpreters; Computer Communication Networks; Special Purpose and Application-Based Systems; Programming Techniques; Software Engineering; Operating Systems

Front Matter....Pages -
The Transmeta Crusoe: VLIW Embedded in CISC....Pages 1-1
Limited Address Range Architecture for Reducing Code Size in Embedded Processors....Pages 2-16
Predicated Instructions for Code Compaction....Pages 17-32
Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation....Pages 33-48
Code Instruction Selection Based on SSA-Graphs....Pages 49-65
A Code Selection Method for SIMD Processors with PACK Instructions....Pages 66-80
Reconstructing Control Flow from Predicated Assembly Code....Pages 81-100
Control Flow Analysis for Recursion Removal....Pages 101-116
An Unfolding-Based Loop Optimization Technique....Pages 117-132
Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer....Pages 133-150
Case Studies on Automatic Extraction of Target-Specific Architectural Parameters in Complex Code Generation....Pages 151-166
Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models....Pages 167-181
A Framework for the Design and Validation of Efficient Fail-Safe Fault-Tolerant Programs....Pages 182-197
A Case Study on a Component-Based System and Its Configuration....Pages 198-210
Composable Code Generation for Model-Based Development....Pages 211-225
Code Generation for Packet Header Intrusion Analysis on the IXP1200 Network Processor....Pages 226-239
Retargetable Graph-Coloring Register Allocation for Irregular Architectures....Pages 240-254
Fine-Grain Register Allocation Based on a Global Spill Costs Analysis....Pages 255-269
Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment....Pages 270-284
Improving Offset Assignment through Simultaneous Variable Coalescing....Pages 285-297
Transformation of Meta-Information by Abstract Co-interpretation....Pages 298-312
Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java....Pages 313-328
Towards Superinstructions for Java Interpreters....Pages 329-343
Partitioning for DSP Software Synthesis....Pages 344-358
Efficient Variable Allocation to Dual Memory Banks of DSPs....Pages 359-372
Cache Behavior Modeling of Codes with Data-Dependent Conditionals....Pages 373-387
FICO: A Fast Instruction Cache Optimizer....Pages 388-402
Back Matter....Pages -