This book discusses single-channel, device-to-device communication in the Internet of Things (IoT) at the signal encoding level and introduces a new family of encoding techniques that result in significant simplifications of the communication circuitry. These simplifications translate into lower power consumption, smaller form factors, and dynamic data rates that are tolerant to clock discrepancies between transmitter and receiver. Readers will be introduced to signal encoding that uses edge-coded signaling, based on the coding of binary data as counts of transmitted pulses. The authors fully explore the far-reaching implications of these novel signal-encoding techniques and illustrate how their usage can help minimize the need for complex circuitries for either clock and data recovery or duty-cycle correction. They also provide a detailed description of a complete ecosystem of hardware and firmware built around edge-code signaling. The ecosystem comprises an application-specific processor, automatic protocol configuration, power and data rate management, cryptographic primitives, and automatic failure recovery modes. The innovative IoT communication link and its associated ecosystem are fully in line with the standard IoT requirements on power, footprint, security, robustness, and reliability.
Author(s): Shahzad Muzaffar, Ibrahim (Abe) M. Elfadel
Publisher: Springer
Year: 2022
Language: English
Pages: 161
City: Cham
Prologue
Acknowledgements
Contents
Abbreviations
1 Introduction
2 Edge-Coded Signaling Techniques
2.1 Edge-Coded Signaling (ECS)
2.1.1 Edge-Coding Scheme
2.1.2 ECS Segmentation
2.1.3 ECS Encoding
2.1.4 ECS Transmitter
Pulse Stream and Separator Generation Scheme
Transmission Flow
2.1.5 ECS Receiver
Pulse Stream and Separator Reception
Reception Flow, Decoding, and Reconstruction
2.1.6 ECS Transmission System
2.1.7 ECS Data Rate
2.2 ECS Optimizations
2.2.1 Optimum Inter-symbol Separator α
2.2.2 Optimum Segment Length l
2.3 Earlier Versions of ECS
2.3.1 Data Rates
2.3.2 Optimizations
2.4 Experimental Setups and Results
2.5 Analysis
2.5.1 Data Rate
2.5.2 Data Word Length and Complexity
Word-Based Implementation
Block-Based Implementation
2.5.3 Error Detection and Correction
2.5.4 Bit Error Rate
2.5.5 Pulse Width and Shape
2.5.6 Reliability
2.5.7 Robustness
2.5.8 Overall Latency
2.5.9 Networking
2.6 Conclusions
3 Timing and Robustness Analysis
3.1 Timing and Robustness Analysis
3.1.1 Sources of Errors
3.1.2 Pulse Width Coefficient
3.1.3 Inter-symbol Separation Coefficient
Inter-symbol Interval Threshold
Selection of Inter-symbol Separation Coefficient
3.1.4 Clock Discrepancy Tolerance
3.1.5 Selection of Inter-symbol Separation Coefficient
3.1.6 Summary on Inter-symbol Separation
3.2 Protocol Failure Modes and Error Correction
3.3 Experimental Verification
3.4 Conclusions
4 Doubling the ECS Data Rate
4.1 Single-Edge Scheme: An Example
4.2 Double Data Rate Edge-Coded Signaling
4.3 Hardware Implementation
4.3.1 Transmitter
4.3.2 Receiver
4.4 Formulation and Optimizations
4.5 Experimental Verification and Results
4.6 Conclusions
5 Power Management
5.1 ECS1 Power Management
5.1.1 Sources of Power Consumption
5.1.2 Proposed ECS1 PHY
Approach
PHY Circuit Implementation
5.1.3 Delay Capacitor
Lower Bound on Delay Capacitance
Upper Bound on Delay Capacitance
5.1.4 Sizing the Pull-Down Resistor
5.1.5 Duty Cycle
5.2 Results
5.2.1 Power Analysis
5.2.2 BER Analysis
5.3 Conclusions
6 Automatic Protocol Configuration
6.1 Automatic Parameter Detection
6.1.1 Algorithm
6.1.2 Inter-symbol Separator Coefficient Calculation
6.1.3 Low-overhead Hardware for αF Calculation
6.2 Experimental Verification
6.3 Conclusions
7 Secure ECS Communication
7.1 Introduction
7.2 Proposed Multilayer Secure Communication Architecture
7.2.1 Re-architecting A5/1 for ECS
Conventional A5/1
Proposed High-Speed A5/1 (HSA5/1)
7.2.2 Secure ECS Communication
Authentication
Confidentiality
Confusion
7.2.3 Multiple Layers of Security
7.3 Example of Secure ECS Communication
7.3.1 Secure Packetization
7.3.2 Secure Reception
7.4 Cryptanalysis of the Multilayer Cipher
7.5 Implementation, Cipher Overhead, and Comparison with Prior Art
7.5.1 Microcontroller Prototype
7.5.2 FPGA Prototype
7.5.3 ASIC Synthesis
7.5.4 Secure ECS Design Alternatives
7.5.5 Comparison with Lightweight Ciphers
7.6 Conclusions
8 Domain-Specific ECS Processor
8.1 Introduction
8.2 Edge-Coded Signaling Interface Architecture (ECSIA)
8.2.1 Register Set
8.2.2 Instruction Formats and Types
Type I
Type II
Type III
8.2.3 Addressing Modes
8.2.4 External I/O and Interrupts
8.2.5 ISA Discussion
8.3 ECSIA Micro-Architecture
8.3.1 Memory Interface
8.3.2 Instruction Decoder
8.3.3 Register File
8.3.4 Clock Distribution and PC Control
8.3.5 Encoder and Select Control (ESC)
8.3.6 Encoder and Selector (ES)
ES Segment Processing
ES in Receiver Mode
ES in Transmitter Mode
8.3.7 Pulse and Delay Generator (PDG)
8.3.8 Pulse Stream Receiver (PSR)
8.3.9 Interrupt Handler
8.3.10 Micro-Architecture Discussion
8.4 Experimental Verification and Results
8.5 Conclusions
9 Application: Hardware Platform for IoT Sensor Networks
9.1 Platform Architecture
9.2 Platform Implementation and Testing
9.2.1 Sensor Nodes
Microcontroller Configuration
I/O Ports Selection
Microcontroller Memories
9.2.2 Multi-Core Debug Control Unit (MCDCU)
On-Chip MCDCU
External MCDCU Daughter Card
9.2.3 Embedded C ECS1 Transceivers
9.2.4 System Integration
9.3 Compiler and Debugging Tools
9.4 Conclusions
10 Application: Body-Coupled Communication
10.1 Introduction
10.2 ECS Signaling and BCC
10.3 BCC Transceiver
10.4 Testing and Verification
10.5 Conclusions
Epilogue
References
Index
