This paper proposes a software mechanism targeting performance profilers which would run at user space privilege to access performance monitoring hardware. The latter requires privileged access in kernel mode, in a secure manner without causing unintended interference to the software stack.
Retrieved from https://software.intel.com/sites/default/files/managed/c5/15/secure-access-performance-monitoring-unit-paper.pdf on 2017 May 09.
Author(s): coll.
Series: Document Number: 334467-001
Edition: Revision 1.0
Publisher: Intel Corporation
Year: 2016
Language: English
Pages: 10
1
2
Introduction ........................................................................................5
1.1
Scope ....................................................................................... 6
Implementation ..................................................................................7
2.1
Security Model ........................................................................... 7
2.2
Access Layer Requirements.......................................................... 7
2.3
Sharing Model ............................................................................ 8
2.4
Architectural Perfmon vs. Model Specific ........................................ 8
2.5
Counter Wrapping ...................................................................... 8
2.6
List of Registers for Secure Access by User-Space Profilers ............... 8
Tables
Table 2-1. Configuration Registers for PMU and Non-PMU Counters ............. 9
Table 2-2. PMU Counter Registers ........................................................... 9
Table 2-3. Other Counter Registers1 .......................................................10
