RISC-V External Debug Support

When a design progresses from simulation to hardware implementation, a user's control and understanding of the system's current state drops dramatically. To help bring up and debug low level software and hardware, it is critical to have good debugging support built into the hardware. When a robust OS is running on a core, software can handle many debugging tasks. However, in many scenarios, hardware support is essential. This document outlines a standard architecture for external debug support on RISC-V platforms. This architecture allows a variety of implementations and trade-offs, which is complementary to the wide range of RISC-V implementations. At the same time, this specification defines common interfaces to allow debugging tools and components to target a variety of platforms based on the RISC-V ISA. System designers may choose to add additional hardware debug support, but this specification defines a standard interface for common functionality.