This book constitutes the refereed proceedings of the Third International Workshop on Applied Reconfigurable Computing, ARC 2007, held in Mangaratiba, Brazil, in March 2007.
The 27 full papers and 10 short papers presented together with a late-comer contribution from ARC 2006 were thoroughly reviewed and selected from 72 submissions. The papers are organized in topical sections on architectures, mapping techniques and tools, arithmetic, and applications.
Author(s): Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev (auth.), Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, João M. P. Cardoso (eds.)
Series: Lecture Notes in Computer Science 4419 : Theoretical Computer Science and General Issues
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2007
Language: English
Pages: 394
Tags: Computer Hardware; Processor Architectures; Computer Communication Networks; System Performance and Evaluation; Computer System Implementation
Front Matter....Pages -
Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array....Pages 1-13
A Configurable Multi-ported Register File Architecture for Soft Processor Cores....Pages 14-25
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture....Pages 26-38
Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture....Pages 39-48
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs....Pages 49-60
Systematic Customization of On-Chip Crossbar Interconnects....Pages 61-72
Authentication of FPGA Bitstreams: Why and How....Pages 73-84
Design of a Reversible PLD Architecture....Pages 85-90
Designing Heterogeneous FPGAs with Multiple SBs....Pages 91-96
Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations....Pages 97-109
Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware....Pages 110-121
Adapting and Automating XILINX’s Partial Reconfiguration Flow for Multiple Module Implementations....Pages 122-129
A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions....Pages 130-141
Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping....Pages 142-154
The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining....Pages 155-166
Hardware/Software Codesign for Embedded Implementation of Neural Networks....Pages 167-178
Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues....Pages 179-190
About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations....Pages 191-200
Switching Activity Models for Power Estimation in FPGA Multipliers....Pages 201-213
Multiplication over $\mathbb{F}_{{p}^{m}}$ on FPGA: A Survey....Pages 214-225
A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm....Pages 226-237
A Fast Finite Field Multiplier....Pages 238-246
Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval....Pages 247-258
Image Processing Architecture for Local Features Computation....Pages 259-270
A Compact Shader for FPGA-Based Volume Rendering Accelerators....Pages 271-282
Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications....Pages 283-292
FPGA-Accelerated Molecular Dynamics Simulations: An Overview....Pages 293-301
Reconfigurable Hardware Acceleration of Canonical Graph Labelling....Pages 302-313
Reconfigurable Computing for Accelerating Protein Folding Simulations....Pages 314-325
Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits....Pages 326-336
A Space Variant Mapping Architecture for Reliable Car Segmentation....Pages 337-342
A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads....Pages 343-349
Searching the Web with an FPGA Based Search Engine....Pages 350-357
An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner’s Dilemma....Pages 358-364
Real Time Architectures for Moving-Objects Tracking....Pages 365-372
Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller....Pages 373-378
Multiple Sequence Alignment Using Reconfigurable Computing....Pages 379-384
Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing....Pages 385-390
Back Matter....Pages -
