Recon?gurable computing (RC) systems have generated considerable interest in the embedded and high-performance computing communities over the past two decades, with ?eld programmable gate arrays (FPGAs) as the leading techn- ogy at the helm of innovation in this discipline. Achieving orders of magnitude performance and power improvements using FPGAs over traditional microp- cessorsis not uncommon for well-suitedapplications. But even with two decades of research and technological advances, FPGA design still presents a subst- tial challenge and often necessitates hardware design expertise to exploit its true potential. Although the challenges to address the design productivity - sues are steep, the promise and the potential of the RC technology in terms of performance, power, size, and versatility continue to attract application design engineers and RC researchers alike. The International Symposium on Applied Recon?gurable Computing (ARC) aims to bring together researchers and practitioners of RC systems with an emphasis on practical applications and design methodologies of this promising technology. This year’s ARC symposium (The sixth ARC symposium) was held in Bangkok, Thailand during March 17–19, 2010, and attracted papers in three primary focus areas:RC applications, RC architectures, and RC design meth- ologies.
Author(s): Ram Krishnamurthy (auth.), Phaophak Sirisuk, Fearghal Morgan, Tarek El-Ghazawi, Hideharu Amano (eds.)
Series: Lecture Notes in Computer Science 5992 : Theoretical Computer Science and General Issues
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2010
Language: English
Pages: 450
Tags: Computer Communication Networks; Algorithm Analysis and Problem Complexity; Software Engineering; Computation by Abstract Devices; Programming Techniques; Simulation and Modeling
Front Matter....Pages I-XIV
High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors....Pages 1-1
Process Variability and Degradation: New Frontier for Reconfigurable....Pages 2-2
Towards Analytical Methods for FPGA Architecture Investigation....Pages 3-3
Generic Systolic Array for Run-Time Scalable Cores....Pages 4-16
Virtualization within a Parallel Array of Homogeneous Processing Units....Pages 17-28
Feasibility Study of a Self-healing Hardware Platform....Pages 29-41
Application-Specific Signatures for Transactional Memory in Soft Processors....Pages 42-54
Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems....Pages 55-67
Parametric Encryption Hardware Design....Pages 68-79
A Reconfigurable Implementation of the Tate Pairing Computation over GF (2 m )....Pages 80-91
Application Specific FPGA Using Heterogeneous Logic Blocks....Pages 92-109
Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip....Pages 110-121
A Dedicated Reconfigurable Architecture for Finite State Machines....Pages 122-133
MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment....Pages 134-144
An FPGA Accelerator for Hash Tree Generation in the Merkle Signature Scheme....Pages 145-156
A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs....Pages 157-168
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods....Pages 169-181
Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA....Pages 182-193
3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices....Pages 194-206
TROUTE: A Reconfigurability-Aware FPGA Router....Pages 207-218
Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing....Pages 219-230
Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture....Pages 231-243
Design Automation for Reconfigurable Interconnection Networks....Pages 244-256
A Framework for Enabling Fault Tolerance in Reconfigurable Architectures....Pages 257-268
QUAD – A Memory Access Pattern Analyser....Pages 269-281
Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations....Pages 282-293
Reconfigurable Computing and Task Scheduling for Active Storage Service Processing....Pages 294-305
A Reconfigurable Disparity Engine for Stereovision in Advanced Driver Assistance Systems....Pages 306-317
A Modified Merging Approach for Datapath Configuration Time Reduction....Pages 318-328
Reconfigurable Computing Education in Computer Science....Pages 329-336
Hardware Implementation of the Orbital Function for Quantum Chemistry Calculations....Pages 337-342
Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing....Pages 343-350
Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures....Pages 351-357
A GMM-Based Speaker Identification System on FPGA....Pages 358-363
An FPGA-Based Real-Time Event Sampler....Pages 364-371
A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster....Pages 372-381
An Analysis of Delay Based PUF Implementations on FPGA....Pages 382-387
Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor....Pages 388-393
FPGA Implementation of QR Decomposition Using MGS Algorithm....Pages 394-399
Memory-Centric Communication Architecture for Reconfigurable Computing....Pages 400-405
Integrated Design Environment for Reconfigurable HPC....Pages 406-413
Architecture-Aware Custom Instruction Generation for Reconfigurable Processors....Pages 414-419
Cost and Performance Evaluation of a Noise Filter for Partitioning in Co-design Methodologies....Pages 420-425
Towards a Tighter Integration of Generated and Custom-Made Hardware....Pages 426-434
Pipelined Microprocessors Optimization and Debugging....Pages 435-444
Back Matter....Pages -
