This book covers advances in Negative Bias Temperature Instability (NBTI) and will prove useful to researchers and professionals in the semiconductor devices areas. NBTI continues to remain as an important reliability issue for CMOS transistors and circuits. Development of NBTI resilient technology relies on utilizing suitable stress conditions, artifact free measurements and accurate physics-based models for the reliable determination of degradation at end-of-life, as well as understanding the process, material and device architectural impacts. This book discusses:
Ultra-fast measurements and modelling of parametric drift due to NBTI in different transistor architectures: planar bulk and FDSOI p-MOSFETs, p-FinFETs and GAA-SNS p-FETs, with Silicon and Silicon Germanium channels. BTI Analysis Tool (BAT), a comprehensive physics-based framework, to model the measured time kinetics of parametric drift during and after DC and AC stress, at different stress and recovery biases and temperature, as well as pulse duty cycle and frequency.
The Reaction Diffusion (RD) model is used for generated interface traps, Transient Trap Occupancy Model (TTOM) for charge occupancy of the generated interface traps and their contribution, Activated Barrier Double Well Thermionic (ABDWT) model for hole trapping in pre-existing bulk gate insulator traps, and Reaction Diffusion Drift (RDD) model for bulk trap generation in the BAT framework; NBTI parametric drift is due to uncorrelated contributions from the trap generation (interface, bulk) and trapping processes.
Analysis and modelling of Nitrogen incorporation into the gate insulator, Germanium incorporation into the channel, and mechanical stress effects due to changes in the transistor layout or device dimensions; similarities and differences of (100) surface dominated planar and GAA MOSFETs and (110) sidewall dominated FinFETs are analysed.
Author(s): Souvik Mahapatra
Publisher: Springer
Year: 2021
Language: English
Pages: 334
City: Singapore
Foreword by Muhammad Ashraful Alam
Foreword by Stephen M. Ramey
Preface
Acknowledgements
Contents
About the Editor
1 Characterization of NBTI Parametric Drift
1.1 Introduction
1.2 NBTI Measurement Methods
1.2.1 Full Sweep MSM Method
1.2.2 One Point Drop Down (OPDD) MSM Method
1.2.3 Other Measurement Methods
1.3 Basic Features of Measured Data
1.3.1 Static (DC) Stress
1.3.2 Dynamic (AC) Stress
1.4 Estimation of EOL Degradation
1.5 Summary
References
2 Device Architecture, Material and Process Dependencies of NBTI Parametric Drift
2.1 Introduction
2.2 Incorporation of Nitrogen
2.3 Si Versus SiGe Channel
2.4 Impact of Mechanical Strain
2.5 Variability in Small Area Devices
2.6 Summary
References
3 Physical Mechanism of NBTI Parametric Drift
3.1 Introduction
3.2 Evidence of Interface Trap Contribution
3.2.1 Charge Pumping (CP) Method
3.2.2 Direct-Current IV (DCIV) Method
3.2.3 Corrections for Measurement Delay and Bandgap
3.3 Evidence of Hole Trapping Contribution
3.3.1 Flicker Noise Measurement
3.3.2 Impact on Time Kinetics and T Activation
3.4 Evidence of Bulk Gate Insulator Trap Generation Contribution
3.5 Summary
References
4 BTI Analysis Tool (BAT) Model Framework—Generation of Interface Traps
4.1 Introduction
4.2 BTI Analysis Tool (BAT) Framework
4.3 Reaction Diffusion (RD) Model
4.3.1 RD Model with Defect-Assisted Dimerization
4.3.2 Physical Mechanism of Interfacial Defect Dissociation
4.4 Experimental Validation of RD model
4.5 Explanation of Process (Ge%, N%) Impact
4.6 Discussion on RD model
4.6.1 Nature of H Passivated Defects (Defect Precursors)
4.6.2 Dissociation of H Passivated Defects
4.6.3 Model Parameters
4.7 Summary
References
5 BTI Analysis Tool (BAT) Model Framework—Interface Trap Occupancy and Hole Trapping
5.1 Introduction
5.2 Interface Trap Generation and Reaction–Diffusion (RD) Model
5.3 Occupancy of Interface Traps
5.3.1 Transient Trap Occupancy Model (TTOM)
5.3.2 Validation of TTOM-Enabled RD model
5.4 Hole Trapping in Preexisting Defects
5.4.1 Activated Barrier Double Well Thermionic (ABDWT) Model
5.4.2 Validation of TTOM-Enabled RD and ABDWT Models
5.5 Multi-segment Arbitrary DC–AC Stress
5.6 Summary
References
6 BTI Analysis Tool (BAT) Model Framework—Generation of Bulk Traps
6.1 Introduction
6.2 Generation of Bulk Gate Insulator Traps
6.2.1 Reaction Diffusion Drift (RDD) Model
6.2.2 Validation of TTOM Enabled RD and RDD Models
6.3 Comparison of FinFET Architectures
6.4 Estimation of EOL Degradation
6.5 Determination of Model Parameters
6.6 Summary
References
7 BAT Framework Modeling of Gate First HKMG Si Channel MOSFETs
7.1 Introduction
7.2 Device Details and Model Parameters
7.3 DC Stress Kinetics—Impact of Nitrogen Incorporation
7.4 DC Stress Kinetics—Impact of Thickness Scaling
7.5 Recovery Kinetics After DC Stress
7.6 Impact of Measurement Delay
7.7 Measurement of Small Area Devices
7.8 Estimation of EOL Degradation
7.9 Summary
References
8 BAT Framework Modeling of Gate First HKMG Si-Capped SiGe Channel MOSFETs
8.1 Introduction
8.2 Device Details and Model Parameters
8.3 Modeling of Stress Kinetics
8.4 Modeling of Recovery Kinetics
8.5 Explanation of Process Dependence
8.5.1 Impact of Si Cap Thickness
8.5.2 Impact of SiGe QW Thickness
8.5.3 Impact of Ge% in SiGe QW
8.6 Estimation of EOL Degradation
8.7 Summary
References
9 BAT Framework Modeling of Gate First HKMG Si and SiGe Channel FDSOI MOSFETs
9.1 Introduction
9.2 Description of Process Splits
9.3 Modeling of Measured Data, Model Parameters
9.3.1 Stress and Recovery Kinetics Over Extended T Range
9.3.2 Impact of Ge% and N%
9.3.3 Impact of Layout (Channel to STI/active Edge Spacing)
9.4 Explanation of Process Dependence
9.4.1 Impact of Ge% and N%
9.4.2 Impact of Layout
9.5 Estimation of EOL Degradation
9.6 Summary
References
10 BAT Framework Modeling of RMG HKMG SOI FinFETs
10.1 Introduction
10.2 Device Details and Model Parameters
10.3 DC Stress Kinetics, Voltage, and Temperature Dependence
10.4 Recovery Kinetics After DC Stress
10.5 AC Stress and Recovery Kinetics
10.6 Variation in Few-Fin FinFETs
10.7 Estimation of EOL Degradation
10.8 Summary
References
11 BAT Framework Modeling of RMG HKMG Si and SiGe Channel FinFETs
11.1 Introduction
11.2 Device Details and Model Parameters
11.3 Stress and Recovery Time Kinetics—DC Stress
11.4 Stress and Recovery Time Kinetics—AC Stress
11.5 Voltage and Temperature Dependence—DC Stress
11.6 Voltage and Temperature Dependence—AC Stress
11.7 Estimation of EOL Degradation
11.8 Summary
References
12 BAT Framework Modeling of RMG HKMG GAA-SNS FETs
12.1 Introduction
12.2 Device Details and Model Parameters
12.3 Description of Model Subcomponents
12.4 Stress and Recovery Time Kinetics
12.5 Voltage and Temperature Dependence
12.6 Estimation of EOL Degradation
12.7 Summary
References
13 BAT Framework Modeling of Dimension Scaling in FinFETs and GAA-SNS FETs
13.1 Introduction
13.2 Device Details and Model Parameters
13.3 Fin Length Scaling in SOI FinFETs
13.4 Fin Length and Width Scaling in SiGe FinFETs
13.5 Sheet Length and Width Scaling in GAA-SNS FETs
13.6 Explanation of Fin and Sheet Dimension Scaling
13.7 Summary
References
14 BAT Framework Modeling of AC NBTI: Stress Mode, Duty Cycle and Frequency
14.1 Introduction
14.2 Device Details and Model Parameters
14.3 Impact of AC Stress Mode, PDC, VGLOW, and Frequency
14.4 Mode-B AC Stress, Impact of PDC and Frequency
14.5 Mode-B AC Stress, Conditions for Frequency Dependence
14.6 Summary
References
Index
