This textbook provides a starter’s guide to VHDL. This book can be used in conjunction with a one-semester course in Digital Systems Design or on its own for designers who only need an introduction to the language. This book is designed to provide a bottoms-up approach to learning the VHDL language. This design supports a course in which foundational knowledge is covered before moving into advanced topics. However, this design also supports use as a reference manual. The author has designed the presentation with learning goals and assessment at its core. Each section addresses a specific learning outcome that the student should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure student performance on each outcome.
Author(s): Brock J. LaMeres
Edition: 2
Publisher: Springer
Year: 2019, 2024
Language: English
Pages: xiii, 255
City: Cham
Tags: Circuits and Systems, Processor Architectures, Logic Design, Digital Design with VHDL,
Preface
Acknowledgments
Contents
1: The Modern Digital Design Flow
1.1 History of Hardware Description Languages
Concept Check
1.2 HDL Abstraction
Concept Check
1.3 The Modern Digital Design Flow
Concept Check
2: VHDL Constructs
2.1 Data Types
2.1.1 Enumerated Types
2.1.2 Range Types
2.1.3 Physical Types
2.1.4 Vector Types
2.1.5 User-Defined Enumerated Types
2.1.6 Array Type
2.1.7 Subtypes
Concept Check
2.2 VHDL Model Construction
2.2.1 Libraries and Packages
2.2.2 The Entity
2.2.3 The Architecture
2.2.3.1 Signal Declarations
2.2.3.2 Constant Declarations
2.2.3.3 Component Declarations
Concept Check
3: Modeling Concurrent Functionality in VHDL
3.1 VHDL Operators
3.1.1 Assignment Operator
3.1.2 Logical Operators
3.1.3 Numerical Operators
3.1.4 Relational Operators
3.1.5 Shift Operators
3.1.6 Concatenation Operator
Concept Check
3.2 Concurrent Signal Assignments with Logical Operators
3.2.1 Logical Operator Example: SOP Circuit
3.2.2 Logical Operator Example: One-Hot Decoder
3.2.3 Logical Operator Example: 7-Segment Display Decoder
3.2.4 Logical Operator Example: One-Hot Encoder
3.2.5 Logical Operator Example: Multiplexer
3.2.6 Logical Operator Example: Demultiplexer
Concept Check
3.3 Conditional Signal Assignments
3.3.1 Conditional Signal Assignment Example: SOP Circuit
3.3.2 Conditional Signal Assignment Example: One-Hot Decoder
3.3.3 Conditional Signal Assignment Example: 7-Segment Display Decoder
3.3.4 Conditional Signal Assignment Example: One-Hot Encoder
3.3.5 Conditional Signal Assignment Example: Multiplexer
3.3.6 Conditional Signal Assignment Example: Demultiplexer
Concept Check
3.4 Selected Signal Assignments
3.4.1 Selected Signal Assignment Example: SOP Circuit
3.4.2 Selected Signal Assignment Example: One-Hot Decoder
3.4.3 Selected Signal Assignment Example: 7-Segment Display Decoder
3.4.4 Selected Signal Assignment Example: One-Hot Encoder
3.4.5 Selected Signal Assignment Example: Multiplexer
3.4.6 Selected Signal Assignment Example: Demultiplexer
Concept Check
3.5 Delayed Signal Assignments
3.5.1 Inertial Delay
3.5.2 Transport Delay
Concept Check
4: Structural Design and Hierarchy
4.1 Components
4.1.1 Component Instantiation
4.1.2 Port Mapping
4.1.2.1 Explicit Port Mapping
4.1.2.2 Positional Port Mapping
Concept Check
4.2 Structural Design Examples: Ripple Carry Adder
4.2.1 Half Adders
4.2.2 Full Adders
4.2.3 Ripple Carry Adder (RCA)
4.2.4 Structural Model of a Ripple Carry Adder in VHDL
Concept Check
5: Modeling Sequential Functionality
5.1 The Process
5.1.1 Sensitivity Lists
5.1.2 Wait Statements
5.1.3 Sequential Signal Assignments
5.1.4 Variables
Concept Check
5.2 Conditional Programming Constructs
5.2.1 If/Then Statements
5.2.2 Case Statements
5.2.3 Infinite Loops
5.2.4 While Loops
5.2.5 For Loops
Concept Check
5.3 Signal Attributes
Concept Check
6: Packages
6.1 STD_LOGIC_1164
6.1.1 STD_LOGIC_1164 Resolution Function
6.1.2 STD_LOGIC_1164 Logical Operators
6.1.3 STD_LOGIC_1164 Edge Detection Functions
6.1.4 STD_LOGIC_1164 Type Conversion Functions
Concept Check
6.2 NUMERIC_STD
6.2.1 NUMERIC_STD Arithmetic Functions
6.2.2 NUMERIC_STD Logical Functions
6.2.3 NUMERIC_STD Comparison Functions
6.2.4 NUMERIC_STD Edge Detection Functions
6.2.5 NUMERIC_STD Conversion Functions
6.2.6 NUMERIC_STD Type Casting
Concept Check
6.3 TEXTIO and STD_LOGIC_TEXTIO
Concept Check
6.4 Other Common Packages
6.4.1 NUMERIC_STD_UNSIGNED
6.4.2 NUMERIC_BIT
6.4.3 NUMERIC_BIT_UNSIGNED
6.4.4 MATH_REAL
6.4.5 MATH_COMPLEX
6.4.6 Legacy Packages (STD_LOGIC_ARITH / UNSIGNED / SIGNED)
Concept Check
7: Test Benches
7.1 Test Bench Overview
Concept Check
7.2 Generating Stimulus Vectors Using For Loops
Concept Check
7.3 Automated Checking Using Report and Assert Statements
7.3.1 Report Statement
7.3.2 Assert Statement
Concept Check
7.4 Using External I/O in Test Benches
7.4.1 Writing to an External File from a Test Bench
7.4.2 Writing to STD_OUTPUT from a Test Bench
7.4.3 Reading from an External File in a Test Bench
7.4.4 Reading Space-Delimited Data from an External File in a Test Bench
Concept Check
8: Modeling Sequential Storage and Registers
8.1 Modeling Scalar Storage Devices
8.1.1 D-Latch
8.1.2 D-Flip-Flop
8.1.3 D-Flip-Flop with Asynchronous Resets
8.1.4 D-Flip-Flop with Asynchronous Reset and Preset
8.1.5 D-Flip-Flop with Synchronous Enable
Concept Check
8.2 Modeling Registers
8.2.1 Registers with Enables
8.2.2 Shift Registers
8.2.3 Registers as Agents on a Data Bus
Concept Check
9: Modeling Finite-State Machines
9.1 The FSM Design Process and a Push-Button Window Controller Example
9.1.1 Modeling the States with User-Defined, Enumerated Data Types
9.1.2 The State Memory Process
9.1.3 The Next-State Logic Process
9.1.4 The Output Logic Process
9.1.5 Explicitly Defining State Codes with Subtypes
Concept Check
9.2 FSM Design Examples
9.2.1 Serial Bit Sequence Detector in VHDL
9.2.2 Vending Machine Controller in VHDL
9.2.3 2-Bit Binary Up/Down Counter in VHDL
Concept Check
10: Modeling Counters
10.1 Modeling Counters with a Single Process
10.1.1 Counters in VHDL Using the Type UNSIGNED
10.1.2 Counters in VHDL Using the Type INTEGER
10.1.3 Counters in VHDL Using the Type STD_LOGIC_VECTOR
Concept Check
10.2 Counters with Enables and Loads
10.2.1 Modeling Counters with Enables
10.2.2 Modeling Counters with Loads
Concept Check
11: Modeling Memory
11.1 Memory Architecture and Terminology
11.1.1 Memory Map Model
11.1.2 Volatile vs. Non-volatile Memory
11.1.3 Read-Only Memory vs. Read/Write Memory
11.1.4 Random Access vs. Sequential Access
Concept Check
11.2 Modeling Read-Only Memory
Concept Check
11.3 Modeling Read/Write Memory
Concept Check
12: Computer System Design
12.1 Computer Hardware
12.1.1 Program Memory
12.1.2 Data Memory
12.1.3 Input/Output Ports
12.1.4 Central Processing Unit
12.1.4.1 Control Unit
12.1.4.2 Data Path: Registers
12.1.4.3 Data Path: Arithmetic Logic Unit (ALU)
12.1.5 A Memory-Mapped System
Concept Check
12.2 Computer Software
12.2.1 Opcodes and Operands
12.2.2 Addressing Modes
12.2.2.1 Immediate Addressing (IMM)
12.2.2.2 Direct Addressing (DIR)
12.2.2.3 Inherent Addressing (INH)
12.2.3 Classes of Instructions
12.2.3.1 Loads and Stores
12.2.3.2 Data Manipulations
12.2.3.3 Branches
Concept Check
12.3 Computer Implementation: An 8-Bit Computer Example
12.3.1 Top-Level Block Diagram
12.3.2 Instruction Set Design
12.3.3 Memory System Implementation
12.3.3.1 Program Memory Implementation in VHDL
12.3.3.2 Data Memory Implementation in VHDL
12.3.3.3 Implementation of Output Ports in VHDL
12.3.3.4 Implementation of Input Ports in VHDL
12.3.3.5 Memory data_out Bus Implementation in VHDL
12.3.4 CPU Implementation
12.3.4.1 Data Path Implementation in VHDL
12.3.4.2 ALU Implementation in VHDL
12.3.4.3 Control Unit Implementation in VHDL
Detailed Execution of LDA_IMM
Detailed Execution of LDA_DIR
Detailed Execution of STA_DIR
Detailed Execution of ADD_AB
Detailed Execution of BRA
Detailed Execution of BEQ
Concept Check
13: Floating-Point Systems
13.1 Overview of Floating-Point Numbers
13.1.1 Limitations of Fixed-Point Numbers
13.1.2 The Anatomy of a Floating-Point Number
13.1.3 The IEEE 754 Standard
13.1.4 Single-Precision Floating-Point Representation (32-Bit)
13.1.5 Double-Precision Floating-Point Representation (64-Bit)
13.1.6 IEEE 754 Special Values
13.1.7 IEEE 754 Rounding Types
13.1.8 Other Capabilities of the IEEE 754 Standard
Concept Check
13.2 IEEE 754 Base Conversions
13.2.1 Converting from Decimal into IEEE 754 Single-Precision Numbers
13.2.2 Converting from IEEE 754 Single-Precision Numbers into Decimal
Concept Check
13.3 Floating-Point Arithmetic
13.3.1 Addition and Subtraction of IEEE 754 Numbers
13.3.2 Multiplication and Division of IEEE 754 Numbers
Concept Check
13.4 Floating-Point Modeling in VHDL
13.4.1 Floating-Point Packages in the IEEE Library
13.4.2 The IEEE_Proposed Library
Concept Check
Appendix A: List of Worked Examples
Index
