This textbook provides a starter’s guide to Verilog, to be used in conjunction with a one-semester course in Digital Systems Design, or on its own for readers who only need an introduction to the language. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the presentation with learning goals and assessment at its core. Each section addresses a specific learning outcome that the student should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure student performance on each outcome.
Author(s): Brock J. LaMeres
Edition: 2
Publisher: Springer
Year: 2023
Language: English
Pages: 238
Preface
Acknowledgments
Contents
1: The Modern Digital Design Flow
1.1 History of Hardware Description Languages
Concept Check
1.2 HDL Abstraction
Concept Check
1.3 The Modern Digital Design Flow
Concept Check
2: Verilog Constructs
2.1 Data Types
2.1.1 Value Set
2.1.2 Net Data Types
2.1.3 Variable Data Types
2.1.4 Vectors
2.1.5 Arrays
2.1.6 Expressing Numbers Using Different Bases
2.1.7 Assigning Between Different Types
Concept Check
2.2 Verilog Module Construction
2.2.1 The Module
2.2.2 Port Definitions
2.2.3 Signal Declarations
2.2.4 Parameter Declarations
2.2.5 Compiler Directives
Concept Check
3: Modeling Concurrent Functionality in Verilog
3.1 Verilog Operators
3.1.1 Assignment Operator
3.1.2 Continuous Assignment
3.1.3 Bitwise Logical Operators
3.1.4 Reduction Logic Operators
3.1.5 Boolean Logic Operators
3.1.6 Relational Operators
3.1.7 Conditional Operators
3.1.8 Concatenation Operator
3.1.9 Replication Operator
3.1.10 Numerical Operators
3.1.11 Operator Precedence
Concept Check
3.2 Continuous Assignment with Logical Operators
3.2.1 Logical Operator Example: SOP Circuit
3.2.2 Logical Operator Example: One-Hot Decoder
3.2.3 Logical Operator Example: 7-Segment Display Decoder
3.2.4 Logical Operator Example: One-Hot Encoder
3.2.5 Logical Operator Example: Multiplexer
3.2.6 Logical Operator Example: Demultiplexer
Concept Check
3.3 Continuous Assignment with Conditional Operators
3.3.1 Conditional Operator Example: SOP Circuit
3.3.2 Conditional Operator Example: One-Hot Decoder
3.3.3 Conditional Operator Example: 7-Segment Display Decoder
3.3.4 Conditional Operator Example: One-Hot Decoder
3.3.5 Conditional Operator Example: Multiplexer
3.3.6 Conditional Operator Example: Demultiplexer
Concept Check
3.4 Continuous Assignment with Delay
Concept Check
4: Structural Design and Hierarchy
4.1 Structural Design Constructs
4.1.1 Lower-Level Module Instantiation
4.1.2 Port Mapping
4.1.2.1 Explicit Port Mapping
4.1.2.2 Positional Port Mapping
4.1.3 Gate Level Primitives
4.1.4 User-Defined Primitives
4.1.5 Adding Delay to Primitives
Concept Check
4.2 Structural Design Example: Ripple Carry Adder
4.2.1 Half Adders
4.2.2 Full Adders
4.2.3 Ripple Carry Adder (RCA)
4.2.4 Structural Model of a Ripple Carry Adder in Verilog
Concept Check
5: Modeling Sequential Functionality
5.1 Procedural Assignment
5.1.1 Procedural Blocks
5.1.1.1 Initial Blocks
5.1.1.2 Always Blocks
5.1.1.3 Sensitivity Lists
5.1.2 Procedural Statements
5.1.2.1 Blocking Assignments
5.1.2.2 Nonblocking Assignments
5.1.3 Statement Groups
5.1.4 Local Variables
Concept Check
5.2 Conditional Programming Constructs
5.2.1 if-else Statements
5.2.2 case Statements
5.2.3 casez and casex Statements
5.2.4 forever Loops
5.2.5 while Loops
5.2.6 repeat Loops
5.2.7 for loops
5.2.8 disable
Concept Check
5.3 System Tasks
5.3.1 Text Output
5.3.2 File Input/Output
5.3.3 Simulation Control and Monitoring
Concept Check
6: Test Benches
6.1 Test Bench Overview
6.1.1 Generating Manual Stimulus
6.1.2 Printing Results to the Simulator Transcript
Concept Check
6.2 Using Loops to Generate Stimulus
Concept Check
6.3 Automatic Result Checking
Concept Check
6.4 Using External Files in Test Benches
Concept Check
7: Modeling Sequential Storage and Registers
7.1 Modeling Scalar Storage Devices
7.1.1 D-Latch
7.1.2 D-Flip-Flop
7.1.3 D-Flip-Flop with Asynchronous Reset
7.1.4 D-Flip-Flop with Asynchronous Reset and Preset
7.1.5 D-Flip-Flop with Synchronous Enable
Concept Check
7.2 Modeling Registers
7.2.1 Registers with Enables
7.2.2 Shift Registers
7.2.3 Registers as Agents on a Data Bus
Concept Check
8: Modeling Finite State Machines
8.1 The FSM Design Process and a Push-Button Window Controller Example
8.1.1 Modeling the States
8.1.2 The State Memory Block
8.1.3 The Next State Logic Block
8.1.4 The Output Logic Block
8.1.5 Changing the State Encoding Approach
Concept Check
8.2 FSM Design Examples
8.2.1 Serial Bit Sequence Detector in Verilog
8.2.2 Vending Machine Controller in Verilog
8.2.3 2-Bit, Binary Up/Down Counter in Verilog
Concept Check
9: Modeling Counters
9.1 Modeling Counters with a Single Procedural Block
9.1.1 Counters in Verilog Using the Type Reg
9.1.2 Counters with Range Checking
Concept Check
9.2 Counter with Enables and Loads
9.2.1 Modeling Counters with Enables
9.2.2 Modeling Counters with Loads
Concept Check
10: Modeling Memory
10.1 Memory Architecture & Terminology
10.1.1 Memory Map Model
10.1.2 Volatile Versus Nonvolatile Memory
10.1.3 Read-Only Versus Read/Write Memory
10.1.4 Random Access Versus Sequential Access
Concept Check
10.2 Modeling Read-Only Memory
Concept Check
10.3 Modeling Read/Write Memory
Concept Check
11: Computer System Design
11.1 Computer Hardware
11.1.1 Program Memory
11.1.2 Data Memory
11.1.3 Input/Output Ports
11.1.4 Central Processing Unit
11.1.4.1 Control Unit
11.1.4.2 Data Path-Registers
11.1.4.3 Data Path-Arithmetic Logic Unit (ALU)
11.1.5 A Memory-Mapped System
Concept Check
11.2 Computer Software
11.2.1 Opcodes and Operands
11.2.2 Addressing Modes
11.2.2.1 Immediate Addressing (IMM)
11.2.2.2 Direct Addressing (DIR)
11.2.2.3 Inherent Addressing (INH)
11.2.3 Classes of Instructions
11.2.3.1 Loads and Stores
11.2.3.2 Data Manipulations
11.2.3.3 Branches
Concept Check
11.3 Computer Implementation-An 8-Bit Computer Example
11.3.1 Top-Level Block Diagram
11.3.2 Instruction Set Design
11.3.3 Memory System Implementation
11.3.3.1 Program Memory Implementation in Verilog
11.3.3.2 Data Memory Implementation in Verilog
11.3.3.3 Implementation of Output Ports in Verilog
11.3.3.4 Implementation of Input Ports in Verilog
11.3.3.5 Memory data_out Bus Implementation in Verilog
11.3.4 CPU Implementation
11.3.4.1 Data Path Implementation in Verilog
11.3.4.2 ALU Implementation in Verilog
11.3.4.3 Control Unit Implementation in Verilog
11.3.4.3.1 Detailed Execution of LDA_IMM
11.3.4.3.2 Detailed Execution of LDA_DIR
11.3.4.3.3 Detailed Execution of STA_DIR
11.3.4.3.4 Detailed Execution of ADD_AB
11.3.4.3.5 Detailed Execution of BRA
11.3.4.3.6 Detailed Execution of BEQ
Concept Check
12: Floating-Point Systems
12.1 Overview of Floating-Point Numbers
12.1.1 Limitations of Fixed-Point Numbers
12.1.2 The Anatomy of a Floating-Point Number
12.1.3 The IEEE 754 Standard
12.1.4 Single-Precision Floating-Point Representation (32-Bit)
12.1.5 Double-Precision Floating-Point Representation (64-Bit)
12.1.6 IEEE 754 Special Values
12.1.7 IEEE 754 Rounding Types
12.1.8 Other Capabilities of the IEEE 754 Standard
Concept Check
12.2 IEEE 754 Base Conversions
12.2.1 Converting from Decimal into IEEE 754 Single-Precision Numbers
12.2.2 Converting from IEEE 754 Single-Precision Numbers into Decimal
Concept Check
12.3 Floating-Point Arithmetic
12.3.1 Addition and Subtraction of IEEE 754 Numbers
12.3.2 Multiplication and Division of IEEE 754 Numbers
Concept Check
12.4 Floating-Point Modeling in Verilog
12.4.1 Modeling Floating-Point Addition in Verilog
12.4.2 Modeling Floating-Point Subtraction in Verilog
12.4.3 Modeling Floating-Point Multiplication in Verilog
12.4.4 Modeling Floating-Point Division in Verilog
Concept Check
Appendix A: List of Worked Examples
Index
