Power-Constrained Testing Of Vlsi Circuits

This book focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the very large scale integrated (VLSI) design flow. After a survey of existing techniques for power constrained testing of VLSI circuits, several test automation techniques are presented for reducing power in scan-based sequential circuits and BIST data paths. Nicolici is affiliated with McMaster University, Canada. Al-Hashimi is affiliated with the University of Southampton, UK.