Aimed at the goal of true single-chip wireless devices, this book provides analyses of challenges involved with the co-integration of active and passive devices in RFIC design, and how modeling parasitic properties during the design phase can minimize undesirable effects such as the de-tuning of RF circuits. The book begins with background on "parasitic-aware" optimization, and then covers topics including monolithic inductors; simulated annealing with tunneling process; particle swarm optimization; and optimization of CMOS low-noise amps, mixers, RF power amps, and CMOS ultra-wideband amps.
Author(s): David J. Allstot, Jinho Park, Kiyong Choi
Edition: 1
Publisher: Springer
Year: 2003
Language: English
Pages: 182
TeamLiB......Page 1
Cover......Page 2
Dedication......Page 7
Contents......Page 9
Contributing Authors......Page 15
Preface......Page 17
PART I: BACKGROUND ON PARASITICAWARE OPTIMIZATION......Page 21
1. INTRODUCTION......Page 23
2. OVERVIEW OF WIRELESS TRANSCEIVERS......Page 25
REFERENCES......Page 27
1.1 Background on monolithic inductors......Page 29
1.2 Monolithic inductor realizations......Page 30
1.3 Monolithic inductor models......Page 31
1.4 Expressions for the lumped inductor model......Page 33
1.6 Monolithic 3- D structures......Page 38
1.5 Monolithic transformers......Page 35
1.7 Parasitic- aware inductor model......Page 40
2.1 Diode varactor......Page 44
2.2 Inversion- mode MOS varactors......Page 45
2.3 Accumulation- mode MOSFET......Page 50
3.1 MOS Transistor High frequency model......Page 51
3.2 Noise model of MOS transistor......Page 54
REFERENCES......Page 56
PARASITIC- AWARE OPTIMIZATION......Page 59
1. GRADIENT DECENT OPTIMIZATION......Page 60
2. SIMULATED ANNEALING......Page 61
3.1 Tunneling process......Page 64
3.2 Local Optimization Algorithm......Page 67
3.3 Adaptive Temp Coefficient Determination......Page 69
3.4 Comparison between SA and ASAT......Page 70
4. GENETIC ALGORITHM ( GA)......Page 72
5.1 Particle swarm optimization algorithm theory......Page 75
5.2 Optimization procedure......Page 79
5.3 Optimization parameters......Page 80
6. POST PVT VARIATION OPTIMIZATION......Page 82
REFERENCES......Page 84
PART II: OPTIMIZATION OF CMOS RF CIRCUITS......Page 85
1.1.1 Thermal noise......Page 87
1.1.2 Noise figure......Page 89
1.2.1 1dB gain compression point......Page 90
1.2.2 Two- tone test ( IIP2 and IIP3)......Page 92
2. DESIGN OF LOW NOISE AMPLIFIER......Page 96
3.1 Calculating gate induced noise in SPICE......Page 100
3.2 Calculating Noise figure in SPICE......Page 101
3.3 Saving optimization time......Page 102
3.6 Optimization Simulation Result......Page 104
REFERENCES......Page 106
1. MIXER......Page 109
2. SINGLE BALANCED MIXER......Page 110
2.1 Conversion gain......Page 111
2.2.1 IIP3......Page 112
2.2.2 Calculating IIP3 and conversion power gain......Page 113
2.3.1 DSB and SSB......Page 115
2.4 LO leakage......Page 116
3. DOUBLE BALANCED MIXER......Page 117
4. DESIGN OF MIXERS......Page 118
5.1 Cost function......Page 119
5.3 Optimization simulation results......Page 120
REFERENCES......Page 124
OPTIMIZATION OF CMOS OSCILLATORS......Page 125
1. CMOS OSCILLATORS......Page 126
2.1 Effects of phase noise......Page 129
2.2 Leeson phase noise model......Page 131
2.3 Hajimiri phase noise model......Page 132
3. DESIGN OF VCO......Page 133
4. OPTIMIZATION OF CMOS VCO......Page 135
4.1 Optimization of VCO......Page 136
4.2 Optimization results......Page 137
REFERENCES......Page 140
1. RF POWER AMPLIFIERS......Page 143
1.1.1 Class- A Power Amplifier......Page 144
1.1.2 Class- B Amplifier......Page 146
1.1.3 Class- C Amplifier and Class- AB Amplifier......Page 147
1.2 Nonlinear power amplifiers: Class- F and Class- E......Page 151
1.2.1 Class- F PA......Page 152
1.2.2 Class- E PA......Page 154
3. OPTIMIZATION OF POWER AMPLIFIER......Page 157
4. POST PVT OPTIMIZATION......Page 161
REFERENCES......Page 164
1.1 Distributed amplification theory......Page 165
1.2 CMOS distributed amplifier......Page 168
1.3 Effects of loss in CMOS distributed amplifiers......Page 169
2. DESIGN OF CMOS ULTRA- WIDEBAND AMPLIFIER......Page 172
3. OPTIMIZATION OF CMOS ULTRA- WIDEBAND AMPLIFIER......Page 175
3.2 Optimization results......Page 176
REFERENCES......Page 178
Index......Page 181
