New software tools and a sophisticated methodology above RTL are required to answer the challenges of designing an optimized application specific processor (ASIP). This book offers an automated and fully integrated implementation flow and compares it to common implementation practice. It provides case-studies that emphasize that neither the architectural advantages nor the design space of ASIPs are sacrificed for an automated implementation.
Author(s): Oliver Schliebusch, Heinrich Meyr, Rainer Leupers
Edition: 1
Publisher: Springer
Year: 2007
Language: English
Pages: 193
Contents......Page 6
Dedication......Page 5
Foreword......Page 9
Preface......Page 11
1.1 From ASIC to ASIP......Page 13
1.2 Heterogeneous Architectures: Computational Performance vs. Flexibility......Page 16
1.3 Challenges of ASIP Design......Page 19
1.4 Organization of This Book......Page 21
2. ASIP DESIGN METHODOLOGIES......Page 22
2.1 ADL based ASIP Design......Page 23
2.2 (Re)Configurable Architectures......Page 28
2.3 Hardware Description Languages and Logic Representation......Page 30
2.4 Motivation of This Work......Page 31
3.1 Design Space Exploration......Page 33
3.2 Software Tools Generation......Page 35
3.3 System Simulation and Integration......Page 38
4. A NEW ENTRY POINT FOR ASIP IMPLEMENTATION......Page 39
4.1 Acceptance Criteria for an Automatic ASIP Implementation......Page 40
4.2 From Architecture to Hardware Description......Page 42
5. LISA FRONTEND......Page 50
5.1 Resource Section......Page 51
5.2 LISA Operations......Page 53
5.3 LISA Operation Graph......Page 54
5.4 Representing Exclusiveness in Conflict and Compatibility Graphs......Page 64
5.5 Exclusiveness Information on the Level of LISA Operations......Page 68
5.6 Exclusiveness Information on the Behavioral Level......Page 73
6.1 Unified Description Layer......Page 75
6.2 Optimization Framework......Page 81
6.3 VHDL, Verilog and SystemC Backend......Page 82
7. OPTIMIZATIONS BASED ON EXPLICIT ARCHITECTURAL INFORMATION......Page 84
7.1 Basic DFG based Optimizations......Page 85
7.2 Resource Sharing......Page 91
7.3 Dependency Minimization......Page 103
7.4 Decision Minimization......Page 105
8.1 Processor Features......Page 107
8.2 JTAG Interface and Debug Mechanism Generation......Page 109
8.3 Adaptability of Synthesis Framework......Page 120
9.1 Turbo Decoding based on Programmable Solutions......Page 122
9.3 The Max-LOGMAP Algorithm......Page 125
9.4 Memory Organization and Address Generation......Page 128
9.6 Instruction Schedule......Page 133
9.7 Pipeline Structure......Page 136
9.8 Results......Page 137
9.9 Concluding Remarks......Page 138
10.1 Levels of Compatibility......Page 140
10.2 The Motorola 68HC11 Architecture......Page 142
10.3 The Infineon Technologies ASMD......Page 149
11. SUMMARY......Page 154
A. Case Studies......Page 157
A.1 ICORE......Page 158
A.2 LT Architecture Family......Page 160
B.1 CFG to DFG Conversion......Page 164
B.2 DFG to CFG Conversion......Page 167
C.1 Advanced Features of Debug Mechanisms......Page 169
List of Figures......Page 173
List of Tables......Page 177
References......Page 178
About the Authors......Page 189
D......Page 191
P......Page 192
Z......Page 193
