OpenSPARC Internals

OpenSPARC Internals......Page 1
Contents......Page 6
Preface......Page 14
Introducing Chip Multithreaded (CMT) Processors......Page 20
OpenSPARC Designs......Page 26
2.2 Commercial Uses for OpenSPARC......Page 27
2.2.3 Coprocessors......Page 28
2.2.4 OpenSPARC as Test Input to CAD/ EDA Tools......Page 29
Architecture Overview......Page 30
3.1.1 Features......Page 31
3.1.2 Attributes......Page 32
3.1.3.1 Binary Compatibility......Page 33
3.2 Processor Architecture......Page 34
3.2.2 Floating-Point Unit (FPU)......Page 35
3.3.1 Memory Access......Page 36
3.3.1.3 Addressing Range......Page 37
3.3.1.5 Separate Instruction and Data Memories......Page 38
3.3.3 Control Transfer......Page 39
3.3.4.2 PR State Registers......Page 40
3.3.8 SIMD......Page 41
3.5 Chip-Level Multithreading (CMT)......Page 42
4.1 General Background......Page 44
4.2 OpenSPARC T1 Overview......Page 46
4.3.1 OpenSPARC T1 Physical Core......Page 48
4.3.2 Floating-Point Unit (FPU)......Page 49
4.3.5 I/O Bridge (IOB) Unit......Page 50
4.3.8 Clock and Test Unit (CTU)......Page 51
4.4 OpenSPARC T2 Overview......Page 52
4.5 OpenSPARC T2 Components......Page 53
4.5.3 Memory Controller Unit (MCU)......Page 54
4.6 Summary of Differences Between OpenSPARC T1 and OpenSPARC T2......Page 55
4.6.2 Instruction Set Architecture (ISA) Differences......Page 56
4.6.3 MMU Differences......Page 58
4.6.5 Error Handling Differences......Page 59
4.6.6 Power Management Differences......Page 60
4.6.7 Configuration, Diagnostic, and Debug Differences......Page 61
OpenSPARC T2 Memory Subsystem - A Deeper Look......Page 62
5.1.2 L1 D-Cache......Page 63
5.1.3 L2 Cache......Page 64
5.2 Memory Controller Unit (MCU)......Page 66
5.3.1 Address Translation Overview......Page 69
5.3.2 TLB Miss Handling......Page 70
5.3.3 Instruction Fetching......Page 71
5.3.4 Hypervisor Support......Page 72
5.3.5.2 Demap Operations......Page 73
5.5 System Interface Unit (SIU)......Page 74
5.7 Memory Models......Page 75
5.8 Memory Transactions......Page 76
5.8.2 Displacement Flushing......Page 77
5.8.4 Cacheable Accesses......Page 78
5.8.6 Global Visibility and Memory Ordering......Page 79
5.8.7 Memory Synchronization: MEMBAR and FLUSH......Page 80
5.8.8 Atomic Operations......Page 81
5.8.9 Nonfaulting Load......Page 82
OpenSPARC Processor Configuration......Page 84
6.1.3 FPGA_SYN_NO_SPU......Page 85
6.2 Changing Level-1 Cache Sizes......Page 86
6.2.1 Doubling the Size of the I-cache......Page 87
6.2.2 Doubling the Number of Ways in the I-cache......Page 88
6.2.3 Changing Data Cache Sizes......Page 89
6.4 Removing the Floating-Point Front-End Unit (FFU)......Page 90
6.5 Adding a Second Floating- Point Unit to the OpenSPARC T2 Core......Page 92
6.6 Changing Level-2 Cache Sizes......Page 93
6.7 Changing the Number of Cores on a Chip......Page 94
6.8.1 Background......Page 95
6.8.2 Implementation......Page 96
6.8.3 Updating the Monitor......Page 97
6.9.1 Background......Page 98
6.9.2 Implementation......Page 100
6.9.3 Caveats......Page 102
OpenSPARC Design Verification Methodology......Page 104
7.1 Verification Strategy......Page 105
7.2 Models......Page 108
7.2.2 Unit-Level Models......Page 109
7.2.3 Full-Chip Model......Page 110
7.3 Verification Methods......Page 111
7.4 Simulation Verification......Page 112
7.4.1 Testbench......Page 113
7.4.2 Assertions......Page 115
7.4.3 Coverage......Page 116
7.4.5 Random Test Generation......Page 118
7.4.6 Result Checking......Page 119
7.5 Formal Verification......Page 120
7.5.2 Property, or Model, Checking......Page 121
7.5.3 Symbolic Simulation......Page 122
7.6 Emulation Verification......Page 123
7.6.1 Emulation Platforms......Page 126
7.6.2 Emulation Deployment......Page 127
7.7 Debugging......Page 129
7.8 Post-Silicon Verification......Page 131
7.8.1 Silicon Validation......Page 132
7.8.2 Silicon Debugging......Page 135
7.8.3 Silicon Bug-Fix Verification......Page 136
7.9 Summary......Page 137
8.1 Virtualization......Page 140
8.3 SPARC Processor Extensions......Page 141
8.4 Operating System Porting......Page 142
9.1.1 Compiling Applications With Sun Studio......Page 144
9.1.3 Improving Performance With Profile Feedback......Page 147
9.1.4 Inlining for Cross-File Optimization......Page 149
9.1.5 Choosing TLB Page Sizes......Page 150
9.2.1 Profiling With Performance Analyzer......Page 151
9.2.2 Gathering Instruction Counts With BIT......Page 156
9.2.3 Evaluating Training Data Quality......Page 161
9.2.4 Profiling With SPOT......Page 165
9.2.5 Debugging With dbx......Page 167
9.2.6 Using Discover to Locate Memory Access Errors......Page 170
9.3 Throughput Computing......Page 171
9.3.1 Measuring Processor Utilization......Page 172
9.3.2 Using Performance Counters to Estimate Instruction and Stall Budget Use......Page 175
9.3.4 Strategies for Parallelization......Page 178
9.3.5 Parallelizing Applications With POSIX Threads......Page 179
9.3.6 Parallelizing Applications With OpenMP......Page 181
9.3.8 Detecting Data Races With the Thread Analyzer......Page 184
9.3.9 Avoiding Data Races......Page 188
9.3.10 Considering Microparallelization......Page 193
9.3.11 Programming for Throughput......Page 196
System Simulation, Bringup, and Verification......Page 198
10.1 SPARC Architecture Model......Page 199
10.1.1 SPARC CPU Model......Page 200
10.1.2 VCPU Interface......Page 201
10.1.2.2 System Interface......Page 202
10.1.3 Module Model Interface......Page 203
10.1.3.3 Module Initialization......Page 204
10.2.1 The sysconf Directive Format......Page 205
10.2.2 Examples......Page 207
10.2.3 Simulated Time in SAM......Page 208
10.3 SAM Huron Sim Architecture......Page 209
10.3.1 Sample Configuration File for T2 Huron on SAM......Page 211
10.3.2 Serial Device Module......Page 212
10.3.3 NCU Module......Page 215
10.3.4 PIU Module......Page 216
10.3.5 IORAM Module......Page 217
10.3.6 Time-of-Day Module......Page 219
10.3.7 PCI-E Bus Module......Page 220
10.3.8 PCIE-PCI Bridge Module......Page 221
10.3.9 PCIE-PCIE Bridge Module......Page 222
10.3.10 Serially Attached SCSI Module......Page 224
10.4 Creation of a Root Disk Image File......Page 227
10.5 Debugging With SAM......Page 229
10.5.1 Simulated State Access......Page 230
10.5.2 Symbol Information......Page 232
10.5.3 Breakpoints......Page 234
10.5.5 Probes......Page 235
10.6.1 Trace-Driven Approach......Page 236
10.6.3 Submodule Approach......Page 237
10.7.1 RTL Cosimulation......Page 238
10.7.1.1 TLB-Sync Model......Page 240
10.7.1.2 LdSt-Sync Model......Page 242
10.7.1.3 Follow-Me Model......Page 244
10.7.2 RTL-SAM Cosimulation Summary......Page 245
OpenSPARC Extension and Modification-Case Study......Page 246
A.1 OpenSPARC T1 Hardware Package......Page 258
A.1.2 Documentation......Page 259
A.1.3 Design Source Code......Page 260
A.1.6 Verification Environment......Page 261
A.2 OpenSPARC T2 Hardware Package......Page 262
A.2.2 Design Source Code......Page 263
A.2.4 Verification Environment......Page 264
A.3 Setup for an OpenSPARC Environment......Page 265
B.1 SPARC Core......Page 268
B.2 L2 Cache......Page 270
B.2.1 L2 Cache Single Bank......Page 271
B.2.2 L2 Cache Instructions......Page 273
B.2.4 L2 Cache Memory Coherency and Instruction Ordering......Page 276
B.4.1 IOB Main Functions......Page 277
B.4.3 IOB Interfaces......Page 278
B.5 Floating-Point Unit (FPU)......Page 279
B.5.1 Floating-Point Instructions......Page 281
B.5.3 Floating-Point Register Exceptions and Traps......Page 282
B.6.1 J-Bus Requests to the L2 Cache......Page 283
B.6.3 J-Bus Interrupt Requests to the IOB......Page 284
Overview of OpenSPARC T2 Design......Page 286
C.1 OpenSPARC T2 Design and Features......Page 287
C.2.1 Instruction Fetch Unit (IFU)......Page 289
C.2.2 Execution Unit......Page 290
C.2.3.2 Functional Units of the LSU......Page 291
C.2.3.3 Special Memory Operation Handling......Page 292
C.3.1 L2 Functional Units......Page 294
C.3.2 L2 Cache Interfaces......Page 296
C.3.3 L2 Cache Instructions......Page 297
C.5 Memory Controller Unit......Page 299
C.5.1 Changes to the OpenSPARC T2 MCU......Page 300
C.5.4 SDRAM Initialization......Page 301
C.6 Noncacheable Unit (NCU)......Page 302
C.6.1 Changes from OpenSPARC T1 I/O Bridge......Page 303
C.7 Floating-Point and Graphics Unit (FGU)......Page 304
C.7.1 FGU Feature Comparison of OpenSPARC T2 and OpenSPARC T1......Page 308
C.7.3 FGU Interfaces......Page 309
C.8 Trap Logic Unit (TLU)......Page 312
C.9 Reliability and Serviceability......Page 314
C.9.2 Core Error Logging......Page 315
C.10 Reset......Page 316
C.12 Debugging Features......Page 318
C.13 Test Control Unit (TCU)......Page 319
C.14 System Interface Unit (SIU)......Page 320
D.1 OpenSPARC T1 Verification Environment......Page 322
D.2 Regression Tests......Page 324
D.2.1 The sims Command Actions......Page 325
D.3.1 Verilog Code Used for Verification......Page 326
D.4 PLI Code Used for the Testbench......Page 328
D.5 Verification Test File Locations......Page 330
D.7 Gate-Level Verification......Page 331
E.1 System Requirements......Page 334
E.2 OpenSPARC T2 Verification Environment......Page 335
E.3 Regression Tests......Page 336
E.4 PLI Code Used For the Testbench......Page 338
E.5 Verification Test File Locations......Page 339
OpenSPARC Resources......Page 340
OpenSPARC Terminology......Page 342
Index......Page 366
Untitled......Page 2