CMOS technologies account for almost 90% of all integrated circuits (ICs). This book provides an essential introduction to nanometer CMOS ICs. The contents of this book are based upon several previous publications and editions entitled 'MOS ICs' and 'Deep-Submicron CMOS ICs'. Nanometer CMOS ICs is fully updated and is not just a copy-and-paste of previous material. It includes aspects of scaling up to and beyond 32nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. In contrast to other works on this topic, the book explores all associated disciplines of nanometer CMOS ICs, including physics, design, technology, yield, packaging, less-power design, variability, reliability and signal integrity. Finally it also includes extensive discussions on the trends and challenges for further scaling. The text is based upon in-house Philips and NXP Semiconductors courseware, which, to date, has been completed by more than 3000 engineers working in a large variety of related disciplines: architecture, design, test, process, packaging, failure analysis and software. Carefully structured and enriched by in-depth exercises, hundreds of colour figures and photographs and many references, the book is well-suited for the purpose of self-study.
Author(s): Harry Veendrick
Edition: 1
Year: 2008
Language: English
Pages: 770
Nanometer CMOS ICs......Page 1
Copyright Page
......Page 4
Foreword......Page 5
Preface......Page 6
Overview of symbols......Page 19
List of physical constants......Page 24
Table of Contents
......Page 25
1.2 The field-effect principle......Page 33
1.3 The inversion-layer MOS transistor......Page 36
1.3.1 The Metal-Oxide-Semiconductor (MOS) capacitor......Page 43
1.3.2 The inversion-layer MOS transistor......Page 47
1.4 Derivation of simple MOS formulae......Page 55
1.5 The back-bias effect (back-gate effect, body effect) and the effect of forward-bias......Page 59
1.6 Factors which characterise the behaviour ofthe MOS transistor......Page 62
1.7 Different types of MOS transistors......Page 64
1.8 Parasitic MOS transistors......Page 66
1.9 MOS transistor symbols......Page 68
1.10 Capacitances in MOS structures......Page 70
1.11 Conclusions......Page 80
1.12 References......Page 81
1.13 Exercises......Page 82
2.1 Introduction......Page 88
2.2 The zero field mobility......Page 89
2.3.1 Vertical and lateral field carrier mobility reduction......Page 90
2.3.2 Stress-induced carrier mobility effects......Page 94
2.4 Channel length modulation......Page 95
2.5.1 Short-channel effects......Page 97
2.5.2 Narrow-channel effect......Page 100
2.6 Temperature influence on carrier mobility and threshold voltage......Page 102
2.7 MOS transistor leakage mechanisms......Page 105
2.7.1 Weak-inversion (subthreshold) behaviour of the MOS transistor......Page 106
2.7.2 Gate-oxide tunnelling......Page 109
2.7.3 Reverse-bias junction leakage......Page 111
2.7.4 Gate-induced drain leakage (GIDL)......Page 112
2.7.5 Impact Ionisation......Page 113
2.7.6 Overall leakage interactions and considerations......Page 114
2.8 MOS transistor models......Page 117
2.9 Conclusions......Page 119
2.10 References......Page 120
2.11 Exercises......Page 122
3.1 Introduction......Page 123
3.2.2 Standard CMOS Epi......Page 125
3.2.3 Crystalline orientation of the silicon wafer......Page 128
3.2.4 Silicon-an-insulator (SOl)......Page 129
3.3.1 Lithography basics......Page 135
3.3.2 Lithographic alternatives beyond 40 nrn......Page 151
3.3.3 Next generation lithography......Page 154
3.3.4 Mask cost reduction techniques for low-volume production......Page 156
Pattern imaging......Page 159
3.4 Etching......Page 161
3.5 Oxidation......Page 164
3.6 Deposition......Page 167
3.7 Diffusion and ion implantation......Page 172
Ion Implantation......Page 173
3.8 Planarisation......Page 176
3.9.1 The basic silicon-gate nMOS process......Page 183
3.9.2 The basic Complementary MOS (CMOS) process......Page 188
Shallow-trench isolation......Page 190
Retrograde-well formation......Page 194
Drain extension......Page 195
Ti/TiN film......Page 196
Damascene metal patterning......Page 197
Devices......Page 198
Interconnects......Page 204
3.10 Conclusions......Page 208
3.11 References......Page 209
3.12 Exercises......Page 213
4.1 Introduction......Page 214
4.2.1 Introduction......Page 215
4.2.2 The DC behaviour......Page 217
Saturated enhancement load transistor......Page 218
The non-saturated enhancement load transistor......Page 219
The depletion load transistor......Page 223
The resistive load......Page 224
4.2.3 Comparison of the different nMOS inverters......Page 225
4.2.4 Transforming a logic function into an nMOS transistor circuit......Page 226
4.3.1 Introduction......Page 229
4.3.2 The CMOS inverter......Page 230
The electrical behaviour of the CMOS inverter......Page 232
Designing a CMOS inverter......Page 236
Dissipation of a CMOS inverter......Page 238
CMOS buffer design......Page 242
4.4.1 Introduction......Page 247
4.4.2 Stat ic CMOS circuits......Page 248
The CMOS transmission gate (pass transistor)......Page 251
Pass-transistor logic......Page 252
Static latches and flip-flops......Page 254
4.4.4 Dynamic CMOS circuits......Page 257
Dynamic CMOS latches, shift registers and flip-flops......Page 259
• Charge sharing......Page 261
• Cross-talk......Page 262
4.4.5 Other types of CMOS circuits......Page 263
Speed and area......Page 264
4.4.7 Clocking strategies......Page 265
4.5.1 CMOS input circuits......Page 266
4.5.2 CMOS output buffers (drivers)......Page 267
4 .6.1 Introduction......Page 269
4.6.2 Layout design rules......Page 270
4.6.3 Stick diagram......Page 274
4.6.4 Example of the layout procedure......Page 277
4.6.5 Guidelines for layout design......Page 281
4.7 Conclusions......Page 283
4.8 References......Page 284
4.9 Exercises......Page 286
5.1 Introduction......Page 290
5.2.2 Basic CCD operation......Page 291
5.2.3 CMOS image sensors......Page 296
5.3.1 Introduction......Page 299
5.3.2 Technology and operation......Page 300
5.3.3 Applications......Page 303
5.4.1 Introduction......Page 304
5.4.2 BICMOS technology......Page 305
5.4.3 BICMOS characteristics......Page 308
5.4.4 BICMOS circuit performance......Page 309
5.4.5 Future expectations and market trends......Page 312
5.5 Conclusions......Page 313
5.6 References......Page 314
5.7 Exercises......Page 316
6.1 Introduction......Page 317
6.2 Serial memories......Page 321
SRAM block diagram......Page 322
The SRAM control signals......Page 325
The SRAM read operation......Page 326
The SRAM write op eration......Page 327
Static RAM cells......Page 328
6.4.3 Dynamic RAMs (DRAM)......Page 338
General remarks on DRAM architectures......Page 347
Fast Page Mode DRAM......Page 349
Synchronous DRAMs......Page 350
6.4.5 Single- and dual port memories......Page 355
6.4.7 Redundancy......Page 356
6.5.2 Read-Only Memories (ROM)......Page 357
ROM cell with the information in the ACTIVE mask......Page 358
ROM cell with the information in the CONTACT mask......Page 360
Comparison of the ACTIVE-mask and CONTACT-mask programmed ROM cells......Page 361
PROMs (Programmable Read-Only Memories)......Page 362
EPROMs......Page 363
EEPROM......Page 365
Flash memories......Page 367
Alternative non-volatile memories and emerging technologies......Page 372
6.5.5 Non-volatile RAM (NVRAM)......Page 373
6.5.7 FRAM, MRAM, PRAM (PCM) and RRAM......Page 374
6.6 Embedded memories......Page 378
6.7 Classification of the various memories......Page 381
6.8 Conclusions......Page 383
6.9 References......Page 385
6.10 Exercises......Page 390
7.1 Introduction......Page 392
7.2 Digital 1Cs......Page 395
7.3.1 Introduction......Page 400
7.3.2 System level......Page 403
7.3.3 Funct ional level......Page 406
7.3.4 RTL level......Page 407
7.3.5 Logic-gate le......Page 410
7.3.6 Transistor level......Page 411
7.3.8 Conclusions......Page 413
7.4.2 The design trajectory and flow......Page 416
7.4.3 Example of synthesis from VHDL description to layout......Page 421
7.5 The use of ASICs......Page 429
7.6.1 Introduction......Page 430
7.6.2 Handcrafted layout implementation......Page 433
7.6.3 Bit-slice layout implementation......Page 434
7.6.4 ROM, PAL and PLA layout implementations......Page 435
7.6.5 Cell-based layout implementation......Page 440
7.6.6 (Mask programmable) gate array layout implementation......Page 442
Field Programmable Gate Arrays (FPGAs)......Page 447
Complex Programmable Logic Devices (CPLDs)......Page 455
7.6.8 Embedded Arrays, Structured ASICs and platform ASICs......Page 461
Structured ASICs and platform ASICs......Page 463
7.6.9 Hierarchical design approach......Page 465
7.6.10 The choice of a layout implementation form......Page 466
7.7 Conciusions......Page 470
7.8 References......Page 471
7.9 Exercises......Page 472
8.1 Introduction......Page 473
8.2 Battery technology summary......Page 474
8.3 Sources of CMOS power consumption......Page 476
8.4.1 Reduction of P1eak by technological measures......Page 478
Active well biasing for leakage power reduction......Page 480
8.4.2 Reduction of Pdyn by technology measures......Page 483
8.4.3 Reduction of Pdyn by reduced-voltage processes......Page 485
8.5.1 Reduction of Pshort by design measures......Page 488
8.5.2 Reduction/elimination of Pstat by design measures......Page 490
Power supply (V) reduction......Page 491
Capacitance reduction......Page 501
Reduction of switching activity......Page 508
Conclusions on number representation......Page 513
8.6 Computing power versus chip power, a scaling perspective......Page 527
8.7 Conclusions......Page 530
8.8 References......Page 531
8.9 Exercises......Page 535
9.1 Introduction......Page 536
9.2.1 Introduction......Page 538
9.2.2 Clock distribution and critical timing issues......Page 539
Single-phase clocking......Page 540
Clock skew and clock jitter......Page 543
Other t iming problems......Page 546
Slack borrowing and time st ea ling......Page 547
On-chip multiple clock generation......Page 548
Clock-phase synchronisation in multiple core environments......Page 550
9.3 Signal integrity......Page 552
9.3.1 Cross-talk and signal propagation......Page 553
9.3.2 Power integrity, supply an ground bounce......Page 560
9.3.3 Substrate bounce......Page 564
9.3.4 EMC......Page 567
9.3.5 Soft errors......Page 568
9.3.6 Signal integrity summary and trends......Page 572
9.4.2 Global vs. local variations......Page 575
9.4.3 Transistor matching......Page 579
9.4.4 From deterministic to probabilistic design......Page 582
9.5 Reliability......Page 584
9.5.2 Electromigration......Page 585
9.5.3 Hot-carrier degradation......Page 588
9.5.4 Negative bias temperature instability (NBTI)......Page 593
9.5.5 Latch-up......Page 594
9.5.6 Electro-Static Discharge (ESD)......Page 598
ESD test models and procedures......Page 599
On-chip ESD protection circuits......Page 601
9.5.8 Reliability summary and trends......Page 603
9.6 Design organisation......Page 604
9.7 Conclusions......Page 606
9.8 References......Page 608
9.9 Exercises......Page 612
10.1 Introduction......Page 614
10.2 Testing......Page 616
10.2.1 Basic LC tests......Page 619
Functional test......Page 620
Delay-fault test......Page 622
Scan test (structural test)......Page 623
Very low voltage (VLV) testing......Page 627
BIST......Page 629
Boundary scan test......Page 632
10.2.2 Design for testability......Page 633
10.3 Yield......Page 635
10.3.1 A simple yield model and yield control......Page 639
10.3.2 Design for manufacturability......Page 645
10.4.1 Introduction......Page 648
10.4.2 Package categories......Page 649
10.4.3 Packaging process flow......Page 652
Backgrinding and sawing......Page 653
Packaging......Page 654
10.4.4 Electrical aspects of packaging......Page 658
10.4.5 Thermal aspects of packaging......Page 660
10.4.6 Reliability aspects of packaging......Page 662
10.4.7 Future trends in packaging technology......Page 664
10.4.8 System-on-a-chip (SoC) versus system-in-a-package (SiP)......Page 666
Quality......Page 670
Reliability......Page 671
10.4.10 Conclusions......Page 672
10.5.1 Problems with testing......Page 673
Gate oxide thickness......Page 675
Polysilicon width......Page 676
Substrate (p-well) and/or n-well dope......Page 677
10.5.3 Problems caused by marginal design......Page 678
10.6.2 Iddq and .6..Iddq testing......Page 679
Diagnosis via Shmoo plots......Page 680
Diagnosis via probing......Page 684
Diagnosis by photon emission microscopy (PEM)......Page 687
10.6.4 More recent debug and failure analysis techniques......Page 689
Time Resolved Photo Emission Microscopy (TR-PEM)......Page 690
Scanning optical beam (SOM) techniques (or laser signal injection microscopy LSIM)......Page 694
Seebeck effect imaging (SEl)......Page 697
Light-induced voltage alteration (LlVA), optical-beam induced current (OBle) and laser-assisted device alteration (LADA)......Page 698
Scanning electron-beam microscopy (SEM) techniques......Page 699
10.6.5 Observing the failure......Page 700
10.6.6 Circuit editing techniques......Page 704
10.6.7 Design for Debug and Design for Failure Analysis......Page 707
10.7 Conclusions......Page 708
10.8 References......Page 709
10.9 Exercises......Page 711
11.1 Introduction......Page 712
11.2 Transistor scaling effects......Page 714
11.3 Interconnection scaling effects......Page 715
11.4 Scaling consequences for overall chip performance and robustness......Page 720
11.5 Potential limitations of the pace of scaling......Page 727
11.6 Conclusions......Page 733
11.7 References......Page 734
11.8 Exercises......Page 735
Index......Page 736
