One of the grand challenges in the nano-scopic computing era is guarantees of robustness. Robust computing system design is confronted with quantum physical, probabilistic, and even biological phenomena, and guaranteeing high reliability is much more difficult than ever before. Scaling devices down to the level of single electron operation will bring forth new challenges due to probabilistic effects and uncertainty in guaranteeing 'zero-one' based computing. Minuscule devices imply billions of devices on a single chip, which may help mitigate the challenge of uncertainty by replication and redundancy. However, such device densities will create a design and validation nightmare with the shear scale. The questions that confront computer engineers regarding the current status of nanocomputing material and the reliability of systems built from such miniscule devices, are difficult to articulate and answer. We have found a lack of resources in the confines of a single volume that at least partially attempts to answer these questions. We believe that this volume contains a large amount of research material as well as new ideas that will be very useful for some one starting research in the arena of nanocomputing, not at the device level, but the problems one would face at system level design and validation when nanoscopic physicality will be present at the device level.
Author(s): Sandeep K. Shukla, R. Iris Bahar
Edition: 1
Publisher: Springer
Year: 2004
Language: English
Commentary: +OCR
Pages: 377
Team DDU......Page 1
Dedication......Page 6
Contents......Page 8
Preface......Page 12
Acknowledgments......Page 16
Part I Nano-Computing at the Physical Layer......Page 20
Preface......Page 22
1.1. Introduction......Page 24
1.2. Silicon Nanoelectronics......Page 25
1.3. Carbon Nanotube Electronics......Page 30
1.4. Molecular Diodes and Switches......Page 46
References......Page 48
Part II Defect Tolerant Nano-Computing......Page 54
Preface......Page 56
2 Nanocomputing in the Presence of Defects and Faults: A Survey......Page 58
2.1. Background......Page 59
2.2. Error Detection, Masking, and Reconfiguration......Page 61
2.3. Non-Traditional Computing Models and Architectures......Page 77
2.4. Tools......Page 83
2.5. Summary......Page 85
References......Page 86
3 Defect Tolerance at the End of the Roadmap......Page 92
3.1. Approaches for Achieving Defect Tolerance in the Nanometer Domain......Page 95
3.2. Technology......Page 97
3.3. Toolflow Required to Achieve Defect Tolerance......Page 101
3.4. Testing......Page 104
3.5. Placement and Routing......Page 119
3.6. Summary......Page 122
References......Page 123
4 Obtaining Quadrillion-Transistor Logic Systems Despite Imperfect Manufacture,Hardware Failure, and Incomplete System Specification......Page 128
4.1. Four Areas for New Research......Page 129
4.2. Cell Matrix Overview......Page 134
4.3. Example of Future Problems: Lower Reliability......Page 139
4.4. Summary, Conclusions......Page 149
References......Page 150
5.1. Introduction......Page 152
5.2. MRF Design for Structural-based Faults......Page 155
5.3. Design for Signal-based Errors......Page 168
5.4. Future Directions......Page 172
References......Page 174
6 Evaluating Reliability Trade-offs for Nano-Architectures......Page 176
6.1. Introduction......Page 177
6.2. Background......Page 181
6.3. Analytical Approaches for Reliability Analysis......Page 192
6.4. NANOLAB: A MATLAB Based Tool......Page 197
6.5. Reliability Analysis of Boolean Networks with NANOLAB......Page 202
6.6. NANOPRISM: A Tool Based on Probabilistic Model Checking......Page 210
6.7. Reliability Analysis of Logic Circuits with NANOPRISM......Page 213
6.8. Reliability Evaluation of Multiplexing Based Majority Systems......Page 218
6.9. Conclusion and Future Work......Page 224
References......Page 226
7.1. Introduction......Page 232
7.2. Background......Page 234
7.3. "Law of Large Numbers" Above the Device Level......Page 235
7.4. Component and System Level LLN in Conventional Systems......Page 236
7.5. Architectures with Sparing......Page 237
7.6. Architectures with Choice......Page 241
7.7. Unique Nanoscale Addressing via Statistical Differentiation......Page 245
7.8. Generalizing Statistical Assembly......Page 246
7.11. Summary......Page 256
References......Page 257
Part III Nano-Scale Quantum Computing......Page 262
Preface......Page 264
8 Challenges in Reliable Quantum Computing......Page 266
8.1. Quantum Computation......Page 268
8.2. Error correction......Page 272
8.3. Quantum Computing Technologies......Page 275
8.4. Fabrication and Test Challenges......Page 277
8.5. Architectural Challenges......Page 279
8.6. Conclusions......Page 282
References......Page 283
9 Origins and Motivations for Design Rules in QCA......Page 286
9.1. The Basic Device and Circuit Elements......Page 287
9.2. Implementable QCA......Page 298
9.3. Design Rules......Page 302
References......Page 311
10 Partitioning and Placement for Buildable QCA Circuits......Page 314
10.1. Preliminaries......Page 315
10.2. Problem Formulation......Page 319
10.3. Zone Partitioning Algorithm......Page 322
10.4. Zone Placement Algorithm......Page 325
10.5. Cell Placement Algorithm......Page 327
10.6. Experimental Results......Page 332
References......Page 335
Part IV Validation of Nano-Scale Architectures......Page 338
Preface......Page 340
11 Verification of Large Scale Nano Systems with Unreliable Nano Devices......Page 342
11.1. Introduction......Page 343
11.2. Scalable Verification of Nano Systems......Page 344
11.3. Scalable Unbounded Model Checking......Page 345
11.4. Scalable Bounded Model Checking......Page 357
11.5. Verification in the Presence of Unknowns and Uncertainties......Page 363
11.6. Summary......Page 366
References......Page 367
Biographies......Page 371
