MT6735 LTE Smartphone Application Processor Functional Specification

Document Revision History
Table of Contents
Preface
Acronyms for register types
1 System Overview
1.1 Highlighted Features Integrated in MT6735
1.2 Platform Features
1.3 Modem Features
1.4 Connectivity Features
1.5 Multimedia Features
1.6 General Description
2 Product Description
2.1 Pin Description
2.1.1 Ball Map View
2.1.2 Pin Coordinate
2.1.3 Detailed Pin Description
2.1.4 Pin Multiplexing, Capability and Settings
2.2 Electrical Characteristic
2.2.1 Absolute Maximum Ratings
2.2.2 Recommended Operating Conditions
2.2.3 Storage Condition
2.2.4 AC Electrical Characteristics and Timing Diagram
2.2.4.1 External Memory Interface for LPDDR3
2.2.4.2 External Memory Interface for LPDDR2
2.3 System Configuration
2.3.1 Mode Selection
2.3.2 Constant Tie Pins
2.4 Power-on Sequence
2.5 Analog Baseband
2.5.1 Introduction
2.5.2 Features
2.5.3 Block Diagram
2.5.3.1 LTE_BBRX
2.5.3.1.1 Block Descriptions
2.5.3.1.2 Functional Specifications
2.5.3.2 C2K_BBRX
2.5.3.2.1 Block Descriptions
2.5.3.3 Functional Specifications
2.5.3.4 LTE_BBTX
2.5.3.4.1 Block Descriptions
2.5.3.4.2 Functional Specifications
2.5.3.5 C2K_BBTX
2.5.3.5.1 Block Descriptions
2.5.3.5.2 Functional Specifications
2.5.3.6 ETDAC
2.5.3.6.1 Block Descriptions
2.5.3.6.2 Functional Specfications
2.5.3.7 APC-DAC
2.5.3.7.1 Block Descriptions
2.5.3.7.2 Functional Specifications
2.5.3.8 AUXADC
2.5.3.8.1 Block Descriptions
2.5.3.8.2 Functional Specifications
2.5.3.9 Clock Squarer
2.5.3.9.1 Block Descriptions
2.5.3.9.2 Functional Specifications
2.5.3.10 Phase Locked Loop
2.5.3.10.1 Block Descriptions
2.5.3.10.2 Functional Specifications
2.5.3.11 Temperature Sensor
2.5.3.11.1 Block Descriptions
2.5.3.11.2 Functional Specifications
2.6 Package Information
2.6.1 Package Outlines
2.6.2 Thermal Operating Specifications
2.6.3 Lead-free Packaging
2.7 Ordering Information
2.7.1 Top Marking Definition
3 MCU and BUS Fabric
3.1 MCU System
3.1.1 Introduction
3.1.2 Features
3.1.2.1 Cluster 0, Cortex-A53 Specifications
3.1.2.2 Clock Modes Between Clusters and AXI Bus Fabric
3.1.3 Interrupt Controller
3.1.4 Register Definition
3.2 On-chip Memory Controller
3.2.1 Introduction
3.2.2 Features
3.2.3 Block Diagram
3.2.3.1 BOOT ROM Power Down Mode
3.2.3.2 BOOT ROM FPC Mode
3.2.3.3 On-Chip SRAM Security Protection
3.2.4 Register Definition
3.3 External Interrupt Controller
3.3.1 Introduction
3.3.2 Features
3.3.3 Block Diagram
3.3.4 Register Definition
3.3.5 Programming Guide
3.3.5.1 Register Bit Set/Clear
3.3.5.2 Domain Control
3.3.5.3 EINT De-bounce Control Sequence
3.4 System Interrupt Controller
3.4.1 Introduction
3.4.2 Features
3.4.3 Block Diagram
3.4.4 Register Definition
3.4.5 Programming Guide
3.4.5.1 MCUSYS MTCMOS Sequence
3.4.5.2 SW Flow
3.5 Infrastructure System Configuration Module
3.5.1 Introduction
3.5.2 Features
3.5.2.1 DCM in Details
3.5.2.2 AXI Fabric Control
3.5.3 Register Definition
3.6 External Memory Interface
3.6.1 Introduction
3.6.2 Features
3.6.3 Block Diagram
3.6.4 Register Definition
3.6.5 Programming Guide
3.7 DRAM Controller
3.7.1 Overview
3.7.2 Features
3.7.2.1 Reference
3.7.3 Block Diagram
3.7.4 Register Definition
3.7.5 Programming Guide
3.8 AP_DMA
3.8.1 Introduction
3.8.2 Features
3.8.3 Block Diagram
3.8.4 Register Definition
3.8.4.1 Global Control Registers
3.8.5 Programming Guide
3.8.5.1 Warm Reset and Hard Reset
3.8.5.2 Pause and Resume
3.9 CQDMA
3.9.1 Introduction
3.9.2 Features
3.9.3 Block Diagram
3.9.4 Register Definition
3.9.4.1 Global Control Registers
4 Clock and Power Control
4.1 Top Clock Generator
4.1.1 Introduction
4.1.2 Features
4.1.3 Block Diagram
4.1.3.1 Clock Architecture
4.1.3.2 Clock Multiplixer
4.1.4 Clock PLL
4.1.5 PLL Related Control
4.1.6 Clock Gating
4.1.7 Frequency Meter
4.1.8 Register Definition
4.1.9 Programming Guide
4.1.9.1 Clock Off
4.1.9.1.1 Clock Switching
4.1.9.1.2 Switch AXI to 26MHz by SCPSYS
4.1.9.1.3 Frequency Meter
4.2 Top Reset Generate Unit
4.2.1 Introduction
4.2.2 Features
4.2.3 Block Diagram
4.2.4 Register Definition
4.2.5 Programming Guide
4.2.5.1 TOPRGU Initial
4.2.5.2 Watchdog Timer
4.2.5.3 IRQ Mode
4.2.5.4 MDSYS and CONNSYS Watchdog Timout
4.2.5.5 Dual Mode Reset
4.2.5.6 DDR Protect
4.2.5.7 DDR Reserved Mode Reset
4.2.5.8 History
4.3 PMIC Wrapper
4.3.1 Introduction
4.3.2 Features
4.3.3 Block Diagram
4.3.4 Register Definition
4.4 Frequency Hopping Controller
4.4.1 Introduction
4.4.2 Features
4.4.3 Block Diagram
4.4.4 Register Definition
5 Peripherals
5.1 Pericfg Controller
5.1.1 Introduction
5.1.2 Features
5.1.3 Block Diagram
5.1.4 Register Definition
5.2 GPIO Control
5.2.1 General Descriptions
5.2.2 Register Definition
5.3 Keypad Scanner
5.3.1 General Description
5.3.2 Waveform
5.3.3 Register Definition
5.4 UART
5.4.1 Introduction
5.4.2 Features
5.4.3 Block Diagram
5.4.4 Register Definition
5.4.5 Programming Guide
5.4.5.1 Auto Baud Rate Detection
5.4.5.2 Transmission
5.5 USB 2.0 High Speed Dual-Role Controller
5.5.1 Introduction
5.5.2 Features
5.5.3 USB Controller Block Diagram
5.5.4 Register Definition
5.5.5 Function Address Register
5.6 USBPHY Register File
5.6.1 Feature List
5.6.2 USBPHY Register File Block Diagram
5.6.3 Register Definition
5.6.4 Function Address Register
5.7 SPI Interface Controller
5.7.1 Introduction
5.7.2 Pin Description
5.7.3 Transmission Formats
5.7.4 Features
5.7.5 Block Diagram
5.7.6 Register Definition
5.7.7 Programming Guide
5.8 MSDC Controller
5.8.1 Introduction
5.8.2 Features
5.8.3 Block Diagram
5.8.4 Register Definition
5.9 AUXADC
5.9.1 Introduction
5.9.2 Features
5.9.3 Block Diagram
5.9.4 Theory of Operation
5.9.4.1 SAR ADC
5.9.4.2 Design Partition
5.9.5 Register Definition
5.10 I2C/SCCB Controller
5.10.1 Introduction
5.10.2 Features
5.10.2.1 Manual Transfer Mode
5.10.2.2 Transfer Format Support
5.10.3 Block Diagram
5.10.4 Register Definition
5.11 Pulse-Width Modulation (PWM)
5.11.1 Introduction
5.11.2 Features
5.11.3 Block Diagram
5.11.4 Register Definition
5.11.5 Clock Source Selection
5.12 General-Purpose Timer (GPT)
5.12.1 Introduction
5.12.2 Features
5.12.3 Block Diagram
5.12.4 Register Definition
5.12.5 Programming Guide
5.13 Thermal Controller
5.13.1 Introduction
5.13.2 Features
5.13.3 Block Diagram
5.13.4 Register Definition
5.13.5 Programming Guide
5.13.5.1 Interrupt Control Flow
5.14 IRTX
5.14.1 Introduction
5.14.2 NEC Protocol
5.14.2.1 Introduction
5.14.2.2 Features
5.14.3 Philips RC-5 Protocol
5.14.3.1 Introduction
5.14.3.2 Features
5.14.4 Philips RC-6 Protocol
5.14.4.1 Introduction
5.14.4.2 Features
5.14.5 Register Definition
5.15 IrDA
5.15.1 Introduction
5.15.2 Features
5.15.3 Block Diagram
5.15.4 Register Definition
5.16 Audio System
5.16.1 Introduction
5.16.2 Features
5.16.3 Block Diagram
5.16.4 Register Definition
6 Multimedia Subsystem
6.1 Multimedia Subsystem
6.1.1 Multimedia Subsystem Configuration
6.1.1.1 Introduction
6.1.1.2 Features
6.1.1.3 Block Diagram
6.1.1.4 Register Definition
6.1.1.5 Programming Guide
6.2 SMI_COMMON
6.2.1 Introduction
6.2.2 Features
6.2.3 Block Diagram
6.2.4 Register Definition
6.3 SMI_LARB
6.3.1 Introduction
6.3.2 Features
6.3.3 Block Diagram
6.3.4 Register Definition
6.4 CAM
6.4.1 Introduction
6.4.2 Features
6.4.3 Register Definition
6.5 SENINF_TOP (Sensor Interface)
6.5.1 Introduction
6.5.2 Features
6.5.3 Register Definition
6.6 FDVT
6.6.1 Module Introduction
6.6.1.1 Overview
6.6.1.2 Theory of Operations
6.6.2 Software Control Flow and Register Settings
6.6.2.1 Software Control Introduction
6.6.3 Parameter Setting in DRAM
6.7 MDP_RDMA
6.7.1 Introduction
6.7.2 Features
6.7.3 Block Diagram
6.7.4 Register Definition
6.7.5 Programming Guide
6.8 MDP RSZ
6.8.1 Introduction
6.8.2 Theory of Operations
6.8.3 Programming Guide
6.8.3.1 Suggested Algorithm
6.8.3.2 Coefficient Step Calculation
6.8.3.3 Input/Output Offset Transfer
6.8.3.4 Table Selection
6.8.3.5 Programming Method
6.8.4 Register Definition
6.9 MDP ROT_DMA (Multimedia Data Path-Rotation DMA)
6.9.1 Introduction
6.9.2 Features
6.9.3 Block Diagram
6.9.4 Register Definition
6.9.5 Programming Guide
6.9.5.1 Firmware Settings for Rotation/Flip
6.9.5.2 Working Buffer Height Setting
6.9.5.3 SMI 256 Byte Boundary Restriction
6.9.5.3.1 Methods to Handle Boundary Restriction
6.9.5.3.2 SMI Boundary Restriction In Case of Rotation
6.10 Display 2D Sharpness
6.10.1 Introduction
6.10.2 Features
6.10.3 Block Diagram
6.10.3.1 2-dimensional Sharpness
6.10.3.2 Peaking by Color
6.10.4 Register Definition
6.10.5 Programming Guide
6.10.5.1 Sharpness Adjustment
6.10.5.2 Luma Adjustment
6.11 DISP_OVL
6.11.1 Introduction
6.11.2 Features
6.11.3 Block Diagram
6.11.4 Register Definition
6.11.5 Programming Guide
6.12 DISP RDMA (Display Read Direct Memory Access)
6.12.1 Introduction
6.12.2 Features
6.12.3 Block Diagram
6.12.4 Register Definition
6.12.5 Programming Guide
6.12.5.1 Memory Mode Control: Raster Scan Input, Progressive Output
6.12.5.2 Memory Mode Control: Raster Scan Input, Interlace Output
6.12.5.3 YUV to RGB Transfer Formula
6.12.5.4 Byte Swap/RGB Swap
6.13 DISP_WDMA
6.13.1 Introduction
6.13.2 Features
6.13.3 Block Diagram
6.13.4 Register Definition
6.13.5 Programming Guide
6.14 Color Processor
6.14.1 Introduction
6.14.2 Features
6.14.3 Block Diagram
6.14.4 Register Definition
6.14.5 Programming Guide
6.14.5.1 Hue Adjustment
6.14.5.2 Luma Adjustment
6.14.5.3 Saturation Adjustment
6.14.5.4 Color Matrix Conversion Programming
6.15 DISP CCORR (Display Color Correction Engine)
6.15.1 Introduction
6.15.2 Features
6.15.3 Block Diagram
6.15.4 Color Correction
6.15.5 Register Definition
6.16 DISP AAL (Display Adaptive Ambient Light Controller)
6.16.1 Introduction
6.16.2 Features
6.16.3 Block Diagram
6.16.4 DRE Enhancement
6.16.5 Register Definition
6.17 DISP GAMMA (Display GAMMA Processing Engine)
6.17.1 Introduction
6.17.2 Features
6.17.3 Gamma correction
6.17.4 Register Definition
6.18 DISP Dither
6.18.1 Introduction
6.18.2 Register Definition
6.19 DISPLAY PWM Generator
6.19.1 Introduction
6.19.2 Features
6.19.3 Register Definition
6.19.4 Programming Guide
6.20 DPI (Digital Parallel Interface)
6.20.1 Introduction
6.20.2 Features
6.20.3 Register Definition
6.20.4 Programming Guide
6.20.4.1 General Timing Programming
6.20.4.2 Data Timing Programming
6.20.4.3 Programming Flow
6.21 Display Serial Interface
6.21.1 Introduction
6.21.2 Features
6.21.3 Register Definition
6.21.4 Programming Guide
6.21.4.1 Clock Control
6.21.4.2 DSI HS Clock Control
6.21.4.3 DSI ULPS Enter Control
6.21.4.4 DSI ULPS Exit Control
6.21.4.5 DPHY Timing Control
6.21.5 Command Mode
6.21.5.1 Command Queue
6.21.5.2 Type-0 Instruction
6.21.5.2.1 Type-1 Instruction
6.21.5.2.2 Type-2 Instruction
6.21.5.2.3 Type-3 Instruction
6.21.5.2.4 Command Mode Status Debug Register
6.21.5.3 Video Mode
6.21.5.3.1 Sync-Pulse Mode
6.21.5.3.2 Sync-Event Mode
6.21.5.3.3 Burst Mode
6.21.5.4 Peripheral TE Detection
6.21.5.4.1 TE Signaling
6.21.5.4.2 External TE Pin
6.21.5.5 Video Mode Extra Packet Transmission
6.21.5.5.1 Short Packet
6.21.5.5.2 Long Packet
6.22 MIPI TX Configuration Module
6.22.1 Introduction
6.22.2 Features
6.22.3 Register Definition
6.22.4 Programming Guide
6.22.4.1 MIPI PLL Initial Sequence
6.22.4.2 MIPI PLL De-initial Sequence
6.22.4.3 Suspend/Resume Control
6.22.5 Software Control Mode
6.22.5.1 MIPI PLL SSC
6.23 JPEG Encoder
6.23.1 Introduction
6.23.2 Features
6.23.2.1 Software Reset Mechanism
6.23.2.2 Byte Offset Address Setting
6.23.3 DRAM Buffer Requirement
6.23.4 Register Definition
6.24 JPEG Decoder
6.24.1 Introduction
6.24.2 Features
6.24.2.1 Software Reset Mechanism
6.24.2.2 Operation Modes
6.24.2.2.1 Normal Mode (Full Frame Mode)
6.24.2.2.2 Pause/Resume Mode
6.24.2.3 Block Resizing
6.24.2.4 Error Handling Mechanism
6.24.3 DRAM Buffer Requirement
6.24.4 Register Definition
6.25 Video Decoder
6.25.1 Introduction
6.25.2 Block Diagram
6.25.2.1 Interface
6.25.3 Programming Guide
6.25.3.1 Base Settings
6.25.3.1.1 Clocks
6.25.3.1.2 VDEC Register Base Address
6.25.3.2 VDEC Hardware Architecture
6.25.3.3 Firmware Hardware Partition
6.25.3.4 FW Decoding Flow
6.25.3.4.1 Software Reset and Power Control Flow
6.25.3.4.2 Turn off VDEC Auto Power Down
6.25.3.4.3 Other Relative Registers for Power Control
6.25.3.4.4 Clock and Power Down Setting
6.25.3.4.5 Interrupt Clear
6.25.3.5 Initial Bitstream DMAs and Barrel-Shifters
6.25.3.5.1 Bitstream FIFO (vb SRAM)
6.25.3.5.2 Barrel Shifter
6.25.3.6 VDEC Output Format
6.25.3.7 VDEC Break Function
6.25.4 VDEC Register Map
6.25.4.1 VDEC_GLOBAL_CON
6.26 H.264 Video Encoder
6.26.1 Introduction
6.26.2 Features
6.26.3 Block Diagram
6.26.4 Register Definition
6.27 MFG
6.27.1 Introduction
6.27.2 Features
6.27.3 Register Definition
6.28 Multimedia Memory Management Unit (M4U)
6.28.1 Introduction
6.28.2 Features
6.28.3 Block Diagram
6.28.4 Register Definition
6.28.5 Programming Guide
7 Analog Baseband
7.1 AP Mixedsys
7.1.1 Block Diagram
7.1.2 Register Definition