MIPS Technologies MIPS32 4K™ Processor Core Family Software User’s Manual

Chapter 1 Introduction to the MIPS32 4K™ Processor Core Family .................................................................
..................1
1.1 Features ...................................................................................................................
................................................2
1.2 Block Diagram ..............................................................................................................
..........................................3
1.3 Required Logic Blocks ......................................................................................................
......................................4
1.3.1 Execution Unit ...........................................................................................................
...................................4
1.3.2 Multiply/Divide Unit (MDU) ...............................................................................................
........................5
1.3.3 System Control Coprocessor (CP0) .........................................................................................
.....................5
1.3.4 Memory Management Unit (MMU) .............................................................................................
................5
1.3.5 Cache Controllers ........................................................................................................
..................................7
1.3.6 Bus Interface Unit (BIU) .................................................................................................
.............................7
1.3.7 Power Management .........................................................................................................
.............................7
1.4 Optional Logic Blocks ......................................................................................................
......................................8
1.4.1 Instruction Cache ........................................................................................................
..................................8
1.4.2 Data Cache ...............................................................................................................
.....................................8
1.4.3 EJTAG Controller .........................................................................................................
................................8
Chapter 2 Pipeline .............................................................................................................
..................................................11
2.1 Pipeline Stages ............................................................................................................
..........................................11
2.1.1 I Stage: Instruction Fetch ...............................................................................................
.............................13
2.1.2 E Stage: Execution .......................................................................................................
...............................13
2.1.3 M Stage: Memory Fetch ....................................................................................................
.........................13
2.1.4 A Stage: Align/Accumulate ................................................................................................
........................13
2.1.5 W Stage: Writeback .......................................................................................................
.............................14
2.2 Instruction Cache Miss .....................................................................................................
.....................................14
2.3 Data Cache Miss ............................................................................................................
.......................................15
2.4 Multiply/Divide Operations .................................................................................................
.................................16
2.5 MDU Pipeline (4Kc and 4Km Cores) ...........................................................................................
........................16
2.5.1 32x16 Multiply (4Kc and 4Km Cores) .......................................................................................
................19
2.5.2 32x32 Multiply (4Kc and 4Km Cores) .......................................................................................
................19
2.5.3 Divide (4Kc and 4Km Cores) ...............................................................................................
......................19
2.6 MDU Pipeline (4Kp Core Only) ...............................................................................................
............................21
2.6.1 Multiply (4Kp Core) ......................................................................................................
.............................21
2.6.2 Multiply Accumulate (4Kp Core) ...........................................................................................
....................22
2.6.3 Divide (4Kp Core) ........................................................................................................
..............................22
2.7 Branch Delay ...............................................................................................................
..........................................23
2.8 Data Bypassing .............................................................................................................
........................................23
2.8.1 Load Delay ...............................................................................................................
...................................24
2.8.2 Move from HI/LO and CP0 Delay ............................................................................................
..................25
2.9 Interlock Handling .........................................................................................................
.......................................25
2.10 Slip Conditions ...........................................................................................................
.........................................26
2.11 Instruction Interlocks ....................................................................................................
......................................27
2.12 Instruction Hazards .......................................................................................................
......................................28
Chapter 3 Memory Management ....................................................................................................
.....................................31
3.1 Introduction ...............................................................................................................
............................................31
3.2 Modes of Operation .........................................................................................................
.....................................32
3.2.1 Virtual Memory Segments ..................................................................................................
........................33
3.2.2 User Mode ................................................................................................................
...................................35
3.2.3 Kernel Mode ..............................................................................................................
.................................36
3.2.4 Debug Mode ...............................................................................................................
.................................38
3.3 Translation Lookaside Buffer (4Kc Core Only) ...............................................................................
....................40
3.3.1 Joint TLB ................................................................................................................
....................................40
3.3.2 Instruction TLB ..........................................................................................................
.................................42
3.3.3 Data TLB .................................................................................................................
...................................43
3.4 Virtual to Physical Address Translation (4Kc Core) .........................................................................
...................43
3.4.1 Hits, Misses, and Multiple Matches .......................................................................................
.....................45
3.4.2 Page Sizes and Replacement Algorithm .....................................................................................
................46
3.4.3 TLB Instructions .........................................................................................................
................................47
3.5 Fixed Mapping MMU (4Km & 4Kp Cores) ........................................................................................
.................47
3.6 System Control Coprocessor .................................................................................................
................................49
Chapter 4 Exceptions ...........................................................................................................
...............................................51
4.1 Exception Conditions .......................................................................................................
.....................................51
4.2 Exception Priority .........................................................................................................
........................................52
4.3 Exception Vector Locations .................................................................................................
.................................53
4.4 General Exception Processing ...............................................................................................
...............................54
4.5 Debug Exception Processing .................................................................................................
...............................55
4.6 Exceptions .................................................................................................................
............................................56
4.6.1 Reset Exception ..........................................................................................................
................................56
4.6.2 Soft Reset Exception .....................................................................................................
..............................57
4.6.3 Debug Single Step Exception ..............................................................................................
.......................58
4.6.4 Debug Interrupt Exception ................................................................................................
..........................59
4.6.5 Non-Maskable Interrupt (NMI) Exception ...................................................................................
..............59
4.6.6 Machine Check Exception (4Kc core) .......................................................................................
.................60
4.6.7 Interrupt Exception ......................................................................................................
...............................60
4.6.8 Debug Instruction Break Exception ........................................................................................
....................60
4.6.9 Watch Exception — Instruction Fetch or Data Access .......................................................................
.......61
4.6.10 Address Error Exception — Instruction Fetch/Data Access .................................................................
....61
4.6.11 TLB Refill Exception — Instruction Fetch or Data Access (4Kc core) ...................................................62
4.6.12 TLB Invalid Exception — Instruction Fetch or Data Access (4Kc core) .................................................63
4.6.13 Bus Error Exception — Instruction Fetch or Data Access ..................................................................
.....63
4.6.14 Debug Software Breakpoint Exception .....................................................................................
...............64
4.6.15 Execution Exception — System Call .......................................................................................
.................64
4.6.16 Execution Exception — Breakpoint ........................................................................................
.................64
4.6.17 Execution Exception — Reserved Instruction ..............................................................................
............64
4.6.18 Execution Exception — Coprocessor Unusable ..............................................................................
.........65
4.6.19 Execution Exception — Integer Overflow ..................................................................................
.............65
4.6.20 Execution Exception — Trap ..............................................................................................
......................65
4.6.21 Debug Data Break Exception ..............................................................................................
......................66
4.6.22 TLB Modified Exception — Data Access (4Kc core) .........................................................................
.....66
4.7 Exception Handling and Servicing Flowcharts ................................................................................
.....................67
Chapter 5 CP0 Registers ........................................................................................................
.............................................73
5.1 CP0 Register Summary .......................................................................................................
..................................73
5.2 CP0 Registers ..............................................................................................................
..........................................75
5.2.1
Index
Register (CP0 Register 0, Select 0) ...........................................................................................
........76
5.2.2
Random
Register (CP0 Register 1, Select 0) ...........................................................................................
...77
5.2.3
EntryLo0
,
EntryLo1
(CP0 Registers 2 and 3, Select 0) ..............................................................................78
5.2.4
Context
Register (CP0 Register 4, Select 0) ...........................................................................................
....80
5.2.5
PageMask
Register (CP0 Register 5, Select 0) ...........................................................................................
81
5.2.6
Wired
Register (CP0 Register 6, Select 0) ...........................................................................................
.......82
5.2.7
BadVAddr
Register (CP0 Register 8, Select 0) ...........................................................................................
83
5.2.8
Count
Register (CP0 Register 9, Select 0) ...........................................................................................
.......84
5.2.9
EntryHi
Register (CP0 Register 10, Select 0) ..........................................................................................
...85
5.2.10
Compare
Register (CP0 Register 11, Select 0) ........................................................................................86
5.2.11
Status
Register (CP0 Register 12, Select 0) ..........................................................................................
....87
5.2.12
Cause
Register (CP0 Register 13, Select 0) ..........................................................................................
....91
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MIPS32 4K™ Processor Core Family Software User’s Manual, Revision 01.17
Copyright © 1998-2002 MIPS Technologies Inc. All right reserved.
5.2.13 Exception Program Counter (CP0 Register 14, Select 0) ...................................................................
......93
5.2.14 Processor Identification (CP0 Register 15, Select 0) ....................................................................
............94
5.2.15
Config
Register (CP0 Register 16, Select 0) ..........................................................................................
...95
5.2.16
Config1
Register (CP0 Register 16, Select 1) ..........................................................................................
.98
5.2.17 Load Linked Address (CP0 Register 17, Select 0) .........................................................................
..........99
5.2.18
WatchLo
Register (CP0 Register 18) ....................................................................................................
..100
5.2.19
WatchHi
Register (CP0 Register 19) ....................................................................................................
..101
5.2.20
Debug
Register (CP0 Register 23) ....................................................................................................
......102
5.2.21 Debug Exception Program Counter Register (CP0 Register 24) ............................................................10
5
5.2.22
ErrCtl
Register (CP0 Register 26, Select 0) ..........................................................................................
.106
5.2.23
TagLo
Register (CP0 Register 28, Select 0) ..........................................................................................
.106
5.2.24
DataLo
Register (CP0 Register 28, Select 1) .........................................................................................1
08
5.2.25
ErrorEPC
(CP0 Register 30, Select 0) ...................................................................................................
109
5.2.26
DeSave
Register (CP0 Register 31) ....................................................................................................
....110
Chapter 6 Hardware and Software Initialization .................................................................................
..............................111
6.1 Hardware Initialized Processor State .......................................................................................
...........................111
6.1.1 Coprocessor Zero State ...................................................................................................
..........................111
6.1.2 TLB Initialization (4Kc core only) .......................................................................................
....................112
6.1.3 Bus State Machines .......................................................................................................
............................112
6.1.4 Static Configuration Inputs ..............................................................................................
.........................112
6.1.5 Fetch Address ............................................................................................................
................................112
6.2 Software Initialized Processor State .......................................................................................
............................112
6.2.1 Register File ............................................................................................................
..................................112
6.2.2 TLB (4Kc Core Only) ......................................................................................................
.........................112
6.2.3 Caches ...................................................................................................................
....................................112
6.2.4 Coprocessor Zero state ...................................................................................................
...........................113
Chapter 7 Caches ...............................................................................................................
................................................115
7.1 Introduction ...............................................................................................................
..........................................115
7.2 Cache Protocols ............................................................................................................
.......................................116
7.2.1 Cache Organization .......................................................................................................
............................116
7.2.2 Cacheability Attributes ..................................................................................................
...........................117
7.2.3 Replacement Policy .......................................................................................................
...........................117
7.3 Instruction Cache ..........................................................................................................
......................................117
7.4 Data Cache .................................................................................................................
.........................................117
7.5 Memory Coherence Issues ....................................................................................................
..............................118
Chapter 8 Power Management .....................................................................................................
.....................................119
8.1 Register-Controlled Power Management .......................................................................................
.....................119
8.2 Instruction-Controlled Power Management ....................................................................................
....................120
Chapter 9 EJTAG Debug Support ..................................................................................................
...................................121
9.1 Debug Control Register .....................................................................................................
.................................122
9.2 Hardware Breakpoints .......................................................................................................
..................................124
9.2.1 Features of Instruction Breakpoint .......................................................................................
.....................124
9.2.2 Features of Data Breakpoint ..............................................................................................
.......................124
9.2.3 Overview of Registers for Instruction Breakpoints ........................................................................
..........125
9.2.4 Registers for Data Breakpoint Setup ......................................................................................
...................126
9.2.5 Conditions for Matching Breakpoints ......................................................................................
.................126
9.2.6 Debug Exceptions from Breakpoints ........................................................................................
................127
9.2.7 Breakpoint used as Triggerpoint ..........................................................................................
.....................129
9.2.8 Instruction Breakpoint Registers .........................................................................................
......................130
9.2.9 Data Breakpoint Registers ................................................................................................
........................136
9.3 Test Access Port (TAP) .....................................................................................................
..................................144
9.3.1 EJTAG Internal and External Interfaces ...................................................................................
................144
9.3.2 Test Access Port Operation ...............................................................................................
........................145
MIPS32 4K™ Processor Core Family Software User’s Manual, Revision 01.17
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Copyright © 1998-2002 MIPS Technologies Inc. All right reserved.
9.3.3 Test Access Port (TAP) Instructions ......................................................................................
...................148
9.4 EJTAG TAP Registers ........................................................................................................
................................150
9.4.1 Instruction Register .....................................................................................................
..............................150
9.4.2 Data Registers Overview ..................................................................................................
........................151
9.4.3 Processor Access Address Register ........................................................................................
..................157
9.4.4 Fastdata Register (TAP Instruction FASTDATA) .............................................................................
......158
9.5 Processor Accesses .........................................................................................................
....................................159
9.5.1 Fetch/Load and Store from/to the EJTAG Probe through dmseg .............................................................16
0
Chapter 10 Instruction Set Overview ............................................................................................
....................................163
10.1 CPU Instruction Formats ...................................................................................................
...............................163
10.2 Load and Store Instructions ...............................................................................................
...............................164
10.2.1 Scheduling a Load Delay Slot ............................................................................................
.....................164
10.2.2 Defining Access Types ...................................................................................................
........................164
10.3 Computational Instructions ................................................................................................
...............................165
10.3.1 Cycle Timing for Multiply and Divide Instructions .......................................................................
........165
10.4 Jump and Branch Instructions ..............................................................................................
.............................166
10.4.1 Overview of Jump Instructions ...........................................................................................
....................166
10.4.2 Overview of Branch Instructions .........................................................................................
...................166
10.5 Control Instructions ......................................................................................................
.....................................166
10.6 Coprocessor Instructions ..................................................................................................
.................................166
10.7 Enhancements to the MIPS Architecture .....................................................................................
.....................166
10.7.1 CLO - Count Leading Ones ................................................................................................
....................167
10.7.2 CLZ - Count Leading Zeros ...............................................................................................
.....................167
10.7.3 MADD - Multiply and Add Word ............................................................................................
..............167
10.7.4 MADDU - Multiply and Add Unsigned Word ..................................................................................
.....167
10.7.5 MSUB - Multiply and Subtract Word .......................................................................................
..............167
10.7.6 MSUBU - Multiply and Subtract Unsigned Word .............................................................................
....167
10.7.7 MUL - Multiply Word .....................................................................................................
.......................168
10.7.8 SSNOP- Superscalar Inhibit NOP ..........................................................................................
................168
Chapter 11 MIPS32 4K Processor Core Instructions ...............................................................................
.........................169
11.1 Understanding the Instruction Descriptions ................................................................................
......................169
11.2 CPU Opcode Map ............................................................................................................
.................................169
11.3 Instruction Set ...........................................................................................................
........................................171
Appendix A Revision History ....................................................................................................
.......................................205
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MIPS32 4K™ Processor Core Family Software User’s Manual, Revision 01.17
Copyright © 1998-2002 MIPS Technologies Inc. All right reserved.
List of Figures
Figure 1-1: 4K Processor Core Block Diagram ....................................................................................
............................... 4
Figure 1-2: Address Translation during a Cache Access in the 4Kc Core ..........................................................
................. 6
Figure 1-3: Address Translation during a Cache Access in the 4Km and 4Kp Cores .................................................
........ 7
Figure 2-1: 4Kc Core Pipeline Stages ...........................................................................................
..................................... 12
Figure 2-2: 4Km Core Pipeline Stages ...........................................................................................
.................................... 12
Figure 2-3: 4Kp Core Pipeline Stages ...........................................................................................
..................................... 12
Figure 2-4: Instruction Cache Miss Timing (4Kc core) ...........................................................................
.......................... 14
Figure 2-5: Instruction Cache Miss Timing (4Km and 4Kp cores)..................................................................
.................. 15
Figure 2-6: Load/Store Cache Miss Timing (4Kc core)............................................................................
......................... 15
Figure 2-7: Load/Store Cache Miss Timing (4Km and 4Kp cores) ...................................................................
................ 16
Figure 2-8: MDU Pipeline Behavior during Multiply Operations (4Kc and 4Km processors) ......................................... 1
8
Figure 2-9: MDU Pipeline Flow During a 32x16 Multiply Operation ................................................................
.............. 19
Figure 2-10: MDU Pipeline Flow During a 32x32 Multiply Operation ...............................................................
............. 19
Figure 2-11: MDU Pipeline Flow During an 8-bit Divide (DIV) Operation ..........................................................
........... 20
Figure 2-12: MDU Pipeline Flow During a 16-bit Divide (DIV) Operation ..........................................................
........... 20
Figure 2-13: MDU Pipeline Flow During a 24-bit Divide (DIV) Operation ..........................................................
........... 20
Figure 2-14: MDU Pipeline Flow During a 32-bit Divide (DIV) Operation ..........................................................
........... 20
Figure 2-15: 4Kp MDU Pipeline Flow During a Multiply Operation.................................................................
............... 22
Figure 2-16: 4Kp MDU Pipeline Flow During a Multiply Accumulate Operation ......................................................
..... 22
Figure 2-17: 4Kp MDU Pipeline Flow During a Divide (DIV) Operation .............................................................
........... 22
Figure 2-18: IU Pipeline Branch Delay ..........................................................................................
.................................... 23
Figure 2-19: IU Pipeline Data Bypass ...........................................................................................
..................................... 24
Figure 2-20: IU Pipeline M to E bypass .........................................................................................
.................................... 24
Figure 2-21: IU Pipeline A to E Data Bypass ....................................................................................
................................ 25
Figure 2-22: IU Pipeline Slip after MFHI .......................................................................................
................................... 25
Figure 2-23: Instruction Cache Miss Slip.......................................................................................
.................................... 26
Figure 3-1: Address Translation During a Cache Access in the 4Kc Core ..........................................................
.............. 32
Figure 3-2: Address Translation During a Cache Access in the 4Km and 4Kp cores .................................................
...... 32
Figure 3-3: 4K Processor Core Virtual Memory Map...............................................................................
......................... 34
Figure 3-4: User Mode Virtual Address Space ....................................................................................
.............................. 35
Figure 3-5: Kernel Mode Virtual Address Space ..................................................................................
............................. 37
Figure 3-6: Debug Mode Virtual Address Space ...................................................................................
............................ 39
Figure 3-7: JTLB Entry (Tag and Data) ..........................................................................................
................................... 41
Figure 3-8: Overview of a Virtual-to-Physical Address Translation in the 4Kc Core ..............................................
......... 44
Figure 3-9: 32-bit Virtual Address Translation .................................................................................
................................. 45
Figure 3-10: TLB Address Translation Flow in the 4Kc Processor Core ............................................................
.............. 46
Figure 3-11: FM Memory Map (ERL=0) in the 4Km and 4Kp Processor Cores ..........................................................
.... 48
Figure 3-12: FM Memory Map (ERL=1) in the 4Km and 4Kp Processor Cores ..........................................................
.... 49
Figure 4-1: General Exception Handler (HW) .....................................................................................
.............................. 68
Figure 4-2: General Exception Servicing Guidelines (SW) ........................................................................
....................... 69
Figure 4-3: TLB Miss Exception Handler (HW) — 4Kc Core only ....................................................................
.............. 70
Figure 4-4: TLB Exception Servicing Guidelines (SW) — 4Kc Core only............................................................
........... 71
Figure 4-5: Reset, Soft Reset and NMI Exception Handling and Servicing Guidelines..............................................
...... 72
Figure 5-1: Wired and Random Entries in the TLB ................................................................................
........................... 82
Figure 7-1: Cache Array Formats ................................................................................................
..................................... 116
Figure 9-1: Instruction Hardware Breakpoint Overview (4Kc Core)................................................................
............... 124
Figure 9-2: Instruction Hardware Breakpoint Overview (4Km and 4Kp Core)........................................................
....... 124
Figure 9-3: Data Hardware Breakpoint Overview (4Kc Core) .......................................................................
................. 125
Figure 9-4: Data Hardware Breakpoint Overview (4Km/4Kp Core) ...................................................................
............ 125
Figure 9-5: TAP Controller State Diagram .......................................................................................
............................... 146
MIPS32 4K™ Processor Core Family Software User’s Manual, Revision 01.17
ix
Copyright © 1998-2002 MIPS Technologies Inc. All right reserved.
Figure 9-6: Concatenation of the EJTAG Address, Data and Control Registers .....................................................
........ 150
Figure 9-7: TDI to TDO Path when in Shift-DR State and FASTDATA Instruction is Selected ................................... 150
Figure 9-8: Endian Formats for the
PAD
Register ........................................................................................................... 158
Figure 10-1: Instruction Formats ...............................................................................................
....................................... 164
Figure 11-1: Usage of Address Fields to Select Index and Way...................................................................
................... 178
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MIPS32 4K™ Processor Core Family Software User’s Manual, Revision 01.17
Copyright © 1998-2002 MIPS Technologies Inc. All right reserved.
MIPS32 4K™ Processor Core Family Software User’s Manual, Revision 01.17
xi
Copyright © 1998-2002 MIPS Technologies Inc. All right reserved.
List of Tables
Table 2-1: 4Kc and 4Km Core Instruction Latencies ..............................................................................
......................... 17
Table 2-2: 4Kc and 4Km Core Instruction Repeat Rates ...........................................................................
........................ 18
Table 2-3: 4Kp Core Instruction Latencies ......................................................................................
................................ 21
Table 2-4: Pipeline Interlocks .................................................................................................
.......................................... 25
Table 2-5: Instruction Interlocks ..............................................................................................
........................................ 27
Table 2-6: Instruction Hazards .................................................................................................
........................................ 28
Table 3-1: User Mode Segments ..................................................................................................
...................................... 36
Table 3-2: Kernel Mode Segments ................................................................................................
..................................... 37
Table 3-3: Physical Address and Cache Attributes for dseg, dmseg, and drseg Address Spaces .....................................
.39
Table 3-4: CPU Access to drseg Address Range ...................................................................................
............................ 39
Table 3-5: CPU Access to dmseg Address Range...................................................................................
........................... 40
Table 3-6: TLB Tag Entry Fields ................................................................................................
....................................... 41
Table 3-7: TLB Data Entry Fields ...............................................................................................
....................................... 42
Table 3-8: TLB Instructions ....................................................................................................
........................................... 47
Table 3-9: Cache Coherency Attributes ..........................................................................................
................................... 47
Table 3-10: Cacheability of Segments with Block Address Translation ............................................................
............... 47
Table 4-1: Priority of Exceptions ..............................................................................................
........................................ 52
Table 4-2: Exception Vector Base Addresses .....................................................................................
............................... 53
Table 4-3: Exception Vector Offsets ............................................................................................
...................................... 54
Table 4-4: Exception Vectors ...................................................................................................
.......................................... 54
Table 4-5: Debug Exception Vector Addresses ....................................................................................
............................. 56
Table 4-6: Register States an Interrupt Exception..............................................................................
................................ 60
Table 4-7: Register States on a Watch Exception ................................................................................
.............................. 61
Table 4-8: CP0 Register States on an Address Exception Error ...................................................................
..................... 62
Table 4-9: CP0 Register States on a TLB Refill Exception .......................................................................
........................ 62
Table 4-10: CP0 Register States on a TLB Invalid Exception .....................................................................
...................... 63
Table 4-11: Register States on a Coprocessor Unusable Exception................................................................
................... 65
Table 4-12: Register States on a TLB Modified Exception ........................................................................
....................... 66
Table 5-1: CP0 Registers .......................................................................................................
............................................ 73
Table 5-2: CP0 Register Field Types ............................................................................................
..................................... 75
Table 5-3: Index Register Field Descriptions...................................................................................
.................................. 76
Table 5-4:
Random
Register Field Descriptions ...................................................................................................
............. 77
Table 5-5:
EntryLo0
,
EntryLo1
Register Field Descriptions ............................................................................................. 78
Table 5-6: Cache Coherency Attributes ..........................................................................................
................................... 78
Table 5-7:
Context
Register Field Descriptions ...................................................................................................
.............. 80
Table 5-8:
PageMask
Register Field Descriptions ...................................................................................................
.......... 81
Table 5-9: Values for the Mask Field of the
PageMask
Register ...................................................................................... 81
Table 5-10: Wired Register Field Descriptions ..................................................................................
................................ 82
Table 5-11:
BadVAddr
Register Field Description ....................................................................................................
........ 83
Table 5-12:
Count
Register Field Description....................................................................................................
................ 84
Table 5-13:
EntryHi
Register Field Descriptions ...................................................................................................
............ 85
Table 5-14:
Compare
Register Field Description ....................................................................................................
.......... 86
Table 5-15:
Status
Register Field Descriptions ...................................................................................................
.............. 88
Table 5-16:
Cause
Register Field Descriptions ...................................................................................................
.............. 91
Table 5-17: Cause Register ExcCode Field Descriptions ..........................................................................
....................... 92
Table 5-18:
EPC
Register Field Description ....................................................................................................
.................. 93
Table 5-19:
PRId
Register Field Descriptions...................................................................................................
................. 94
Table 5-20:
Config
Register Field Descriptions ...................................................................................................
............. 95
Table 5-21: Cache Coherency Attributes .........................................................................................
.................................. 96
Table 5-22:
Config1
Register Field Descriptions — Select 1 ........................................................................................
... 98
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MIPS32 4K™ Processor Core Family Software User’s Manual, Revision 01.17
Copyright © 1998-2002 MIPS Technologies Inc. All right reserved.
Table 5-23:
LLAddr
Register Field Descriptions ...................................................................................................
............ 99
Table 5-24:
WatchLo
Register Field Descriptions ...................................................................................................
........ 100
Table 5-25:
WatchHi
Register Field Descriptions ...................................................................................................
........ 101
Table 5-26:
Debug
Register Field Descriptions ...................................................................................................
........... 102
Table 5-27:
DEPC
Register Formats..............................................................................................................
.................. 105
Table 5-28:
ErrCtl
Register Field Descriptions ...................................................................................................
............ 106
Table 5-29:
TagLo
Register Field Descriptions ...................................................................................................
............ 107
Table 5-30:
DataLo
Register Field Description ....................................................................................................
........... 108
Table 5-31:
ErrorEPC
Register Field Description....................................................................................................
....... 109
Table 5-32:
DeSave
Register Field Description ....................................................................................................
........... 110
Table 7-1: Instruction and Data Cache Attributes ...............................................................................
............................ 115
Table 7-2: Instruction and Data Cache Sizes ....................................................................................
.............................. 116
Table 9-1:
Debug Control Register
Field Descriptions ................................................................................................... 122
Table 9-2: Overview of Status Register for Instruction Breakpoints .............................................................
................. 125
Table 9-3: Overview of Registers for each Instruction Breakpoint ...............................................................
................. 125
Table 9-4: Overview of Status Register for Data Breakpoints ....................................................................
..................... 126
Table 9-5: Overview of Registers for each Data Breakpoint ......................................................................
..................... 126
Table 9-6: Addresses for Instruction Breakpoint Registers ......................................................................
....................... 130
Table 9-7:
IBS
Register Field Descriptions ...................................................................................................
................... 131
Table 9-8:
IBAn
Register Field Descriptions...................................................................................................
................. 132
Table 9-9:
IBMn
Register Field Descriptions...................................................................................................
................ 133
Table 9-10:
IBASIDn
Register Field Descriptions ...................................................................................................
........ 134
Table 9-11:
IBCn
Register Field Descriptions ...................................................................................................
.............. 135
Table 9-12: Addresses for Data Breakpoint Registers ............................................................................
......................... 136
Table 9-13:
DBS
Register Field Descriptions ...................................................................................................
............... 137
Table 9-14:
DBAn
Register Field Descriptions ...................................................................................................
............. 138
Table 9-15:
DBMn
Register Field Descriptions ...................................................................................................
............ 139
Table 9-16:
DBASIDn
Register Field Descriptions ...................................................................................................
....... 140
Table 9-17:
DBCn
Register Field Descriptions ...................................................................................................
............ 141
Table 9-18:
DBVn
Register Field Descriptions ...................................................................................................
............. 143
Table 9-19: EJTAG Interface Pins ...............................................................................................
................................... 144
Table 9-20: Implemented EJTAG Instructions .....................................................................................
........................... 148
Table 9-21: Device Identification Register .....................................................................................
................................. 152
Table 9-22:
Implementation
Register Descriptions .........................................................................................................
. 152
Table 9-23:
EJTAG Control
Register Descriptions .........................................................................................................
153
Table 9-24: Fastdata Register Field Description ................................................................................
............................. 158
Table 9-25: Operation of the FASTDATA access ...................................................................................
....................... 159
Table 10-1: Byte Access within a Word..........................................................................................
................................. 165
Table 11-1: Encoding of the Opcode Field .......................................................................................
............................... 169
Table 11-2: Special Opcode Encoding of Function Field ..........................................................................
...................... 170
Table 11-3: Spedial2 Opcode Encoding of Function Field .........................................................................
..................... 170
Table 11-4: RegImm Encoding of rt Field ........................................................................................
............................... 170
Table 11-5: COP0 Encoding of rs Field ..........................................................................................
................................. 170
Table 11-6: COP0 Encoding of Function Field When rs=CO .........................................................................
................ 171
Table 11-7: Instruction Set ....................................................................................................
.......................................... 171
Table 11-8: Usage of Effective Address .........................................................................................
................................. 177
Table 11-9: Encoding of Bits[17:16] of CACHE Instruction .......................................................................
................... 178
Table 11-10: Encoding of Bits [20:18] of the CACHE Instruction ErrCtl[WST,SPR] Cleared ...................................... 179
Table 11-11: Encoding of Bits [20:18] of the CACHE Instruction, ErrCtl[WST] Set. ErrCtl[SPR] Cleared ................. 181
Table 11-12: Encoding of Bits [20:18] of the CACHE Instruction, ErrCtl[SPR] Set................................................
...... 182
Table 11-13: Values of the
hint
Field for the PREF Instruction ....................................................... 188