MIPI Specification for M-PHY Version 2.0

Contents......Page 5
Figures......Page 9
Tables......Page 12
Release History......Page 14
1.1 Scope......Page 15
1.2 Purpose......Page 16
2.1 Definitions......Page 17
2.3 Acronyms......Page 19
3 References......Page 21
4.1 PIN, LINE, LANE, SUB-LINK, LINK, and M-PORT......Page 22
4.2 LINE States......Page 23
4.3 Signaling Schemes......Page 24
4.4 Overview of Concept, Features, and Options......Page 25
4.5.1 Data Symbols......Page 27
4.5.2 Control Symbols......Page 29
4.5.3.2 M-RX Disparity Handling......Page 30
4.6 State Machines......Page 31
4.6.1 State Machine for a Type-I MODULE......Page 32
4.6.2 State Machine for a Type-II MODULE......Page 33
4.6.3 State Machine Structure and State Categories......Page 35
4.7.1.2 SLEEP......Page 36
4.7.1.3 HIBERN8......Page 37
4.7.1.5.1 Power-Up Cycle......Page 38
4.7.2 BURST States......Page 40
4.7.2.2 SYNC......Page 41
4.7.2.4.2 Closure and Return to LINE-CFG......Page 45
4.7.2.5 Example of an HS-BURST......Page 46
4.7.3.2.1 PWM-GEARs......Page 48
4.7.3.3 System-clock Synchronous BURST (SYS-BURST)......Page 49
4.7.4.2 LINE-CFG (Type-I MODULE Only)......Page 50
4.7.4.2.2 LINE Control Command (LCC)......Page 52
4.7.4.2.4 Re-Configuration Trigger (RCT)......Page 54
4.8.1 Conceptual Configuration Process......Page 55
4.8.1.2 Configuration with Media Converters in the LINE......Page 56
4.8.2 Configuration Parameters......Page 57
4.10.1 LOOPBACK Mode......Page 58
5.1.1.1 PIN, Signal, and Reference Characteristic Definitions......Page 60
5.1.1.2 Differential and Common-mode Voltage......Page 64
5.1.1.3 Single-ended Output Resistance......Page 65
5.1.1.4 Return Loss......Page 66
5.1.1.6 Common M-TX Parameters......Page 67
5.1.2 HS-TX Characteristics......Page 68
5.1.2.3 Intra-LANE Output Skew......Page 69
5.1.2.6 Transmitter Pulse Width......Page 70
5.1.2.7 Transmitter Jitter......Page 71
5.1.2.9 Power Spectral Magnitude Limit......Page 72
5.1.2.9.2 Spectrum Generation Method......Page 73
5.1.2.11 HS-TX Parameters......Page 74
5.1.3 PWM-TX Characteristics......Page 75
5.1.3.1 PWM Bit Duration, Bit Duration Tolerance, and Ratio......Page 76
5.1.3.4 PWM-TX Parameters......Page 77
5.1.4.2 LANE-to-LANE Skew......Page 78
5.2.1.1 PIN, Signal, and Reference Characteristic Definitions......Page 79
5.2.1.2 Differential and Common-mode Voltage......Page 81
5.2.1.4 Differential Termination Switching Time......Page 82
5.2.2 Common M-RX Parameters......Page 83
5.2.3.2 Receiver Jitter Tolerance......Page 84
5.2.3.3 Receiver Eye Opening and Accumulated Differential Receiver Input Voltage......Page 85
5.2.3.5 HS-RX Parameters......Page 86
5.2.4.2 PWM Bit Duration, Bit Duration Tolerance, and Ratio......Page 88
5.2.4.5 PWM-RX Parameters......Page 89
5.2.6.1 Squelch Common-mode Voltage and Squelch Differential Voltage......Page 91
5.2.6.4 Squelch Pulse and RF Rejection......Page 92
5.3.1 PIN Capacitance......Page 93
5.3.5 PIN Parameters......Page 94
6.2 Methodology......Page 95
6.3.2 Simulation Environment Setup......Page 96
7.3 Internal and External OMCs......Page 98
7.4 OMC – Architecture and Operations......Page 99
7.4.3.1 Power Supply Removal......Page 100
7.5 OMC – Electrical and Interconnect......Page 101
7.5.2.2 OMC – Signal Propagation Delay......Page 102
7.5.3.1 OMC – HS-BURST Timing......Page 103
7.5.3.2 OMC – HS-BURST Jitter Budget......Page 104
7.6.1.1 Basic OMC......Page 105
7.6.2 OMC – Configuration LCCs......Page 106
7.6.2.1 OMC – LCC-WRITE......Page 107
7.6.2.1.1 OMC – LCC-WRITE-ATTRIBUTE......Page 108
7.6.2.1.2 OMC – LCC-WRITE-CUSTOM......Page 109
7.6.2.2.1 OMC – LCC-READ-CAPABILITY......Page 110
7.6.2.2.2 OMC – LCC-READ-MFG-INFO and LCC-READ-VEND-INFO......Page 111
7.7 OMC – M-PHY Conformance......Page 112
7.8 OMC – Test Methodology......Page 113
8.1 Service Primitive Naming Convention......Page 114
8.2 M-TX-DATA and M-RX-DATA SAP......Page 115
8.2.1.1 Semantics of the Service Primitive......Page 116
8.2.1.2 When Generated......Page 117
8.2.2.1 Semantics of the Service Primitive......Page 118
8.2.2.2 When Generated......Page 119
8.2.3.3 Effect on Receipt......Page 120
8.2.6.1 Semantics of the Service Primitive......Page 121
8.2.8 M-LANE-SYNC.confirm......Page 122
8.2.10.2 When Generated......Page 123
8.2.12.2 When Generated......Page 124
8.2.14 Sequence of Service Primitives......Page 125
8.3 M-TX-CTRL SAP and M-RX-CTRL SAP......Page 126
8.3.1.1 Semantics of the Service Primitive......Page 127
8.3.3.2 When Generated......Page 128
8.3.5.2 When Generated......Page 129
8.3.8 M-CTRL-RESET.confirm......Page 130
8.3.10.1 Semantics of the Service Primitive......Page 131
8.3.12.3 Effect on Receipt......Page 132
8.4 M-TX and M-RX Attributes......Page 133
A.2 The M-RX Signaling Interface......Page 154
A.2.1 M-RX Signal Description......Page 155
A.3.1 M-TX Signal Description......Page 163
A.4.1 Attribute Read from Effective Configuration......Page 169
A.4.3 Effective Configuration Single-step Update and Local RESET......Page 170
A.4.4 Received LCC and LINE-RESET......Page 171
A.4.5 HS Data Reception with 20-bit RX_Symbol Bus......Page 173
A.4.6 TX_LineReset Behavior......Page 174
A.4.7 HS Transmission on 20-bit TX_Symbol Bus with Data Throttled by Protocol Layer......Page 175
A.4.8 HS Transmission on 20-bit TX_Symbol Bus with Data Throttled by M-TX......Page 176
B.1.1 General Transmitter Test Approach......Page 178
B.1.4 Continuous vs. Burst Modes......Page 179
B.2.2 Loopback Mode......Page 180
B.2.3 Receiver Pattern Checking......Page 181
B.3 Interoperability Testing......Page 182
C.1.1 Dither Magnitude......Page 183
D.1 Attribute Pair Matching for MODULEs of a LANE......Page 185
D.3.2 TX_PWM_BURST_Closure_Extension......Page 186
D.3.3 TX_DRIVER_POLARITY......Page 187
Annex E Guidance for Protocols on Managing LANE-to-LANE Skew (informative)......Page 188