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Low-Power High-Speed Adcs For Nanometer Cmos Integration

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Low-Power High-Speed ADCs for Nanometer CMOS Integration is about designing ADCs in nanometer CMOS processes to achive lower power consumption for a given speed and resolution than previous designs through new architectures and circuits that take advantage of unique features of nanometer CMOS processes.

Author(s): Zhiheng Cao, Shouli Yan
Series: Analog Circuits and Signal Processing
Edition: 1st Edition.
Publisher: Springer
Year: 2010

Language: English
Commentary: 49465
Pages: 103