Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.
Author(s): Zhiheng Cao, Shouli Yan
Series: ANALOG CIRCUITS AND SIGNAL PROCESSING
Edition: 1
Publisher: Springer
Year: 2008
Language: English
Pages: 103
Contents......Page 8
Preface......Page 6
List of Tables......Page 10
List of Figures......Page 11
1.1.1 Analog-to-Digital Converters......Page 14
1.2.1 Flash......Page 16
1.2.2 Pipeline......Page 17
1.2.3 Subranging......Page 18
1.2.4 Successive Approximation......Page 19
1.2.5 ΔΣ ADCs......Page 21
2.1 Background......Page 23
2.2 Architecture and Circuits......Page 24
2.2.1 Capacitor Sampling Network/5 b-DAC......Page 27
2.2.2 Conversion Timing Diagram......Page 29
2.2.3 Sampling Clock Skew Calibration......Page 30
2.2.4 6 b Fine ADC......Page 32
2.2.6 5 b Coarse ADC......Page 37
2.3 Experimental Results......Page 39
2.3.1 Test Setup......Page 40
2.3.2 Characterization of the Clock Delay Line......Page 43
2.3.3 ADC Measurement Results......Page 44
2.4 Summary......Page 51
3.1 Background......Page 52
3.2 Architecture......Page 53
3.3.1 Fast Settling Capacitor-Network......Page 57
3.3.2 Flip-Flop Bypass SAR Logic......Page 59
3.3.3 Digital Background Offset Correction......Page 61
3.3.4 High-Speed Low-Hysteresis Comparator......Page 63
3.3.5 Floor Plan and Layout Considerations......Page 66
3.4.1 Capturing ADC Output Data......Page 68
3.4.2 Serial Configuration Interface......Page 70
3.4.3 Test Setup......Page 71
3.4.4 Evaluation Board Design......Page 72
3.5.1 Summary of Results and Discussions......Page 73
3.6 Performance Summary and Comparison......Page 76
3.7 Summary......Page 77
4.1 Introduction......Page 79
4.2.1 Phase-to-Voltage Converter and Loop Filter......Page 81
4.2.2 Phase Error Preamplification......Page 84
4.2.3 Constant Loop-Bandwidth Biasing......Page 85
4.3.1 Phase Noise and Power Consumption Programmability......Page 86
4.3.2 VCO Buffer with 50% Duty Cycle Output......Page 88
4.4.1 Test Setup......Page 90
4.4.2 Measurement Results and Discussion......Page 92
4.4.3 Comparison with Existing PLLs with Similar Output Frequency Range......Page 93
4.5 Summary......Page 97
5. Conclusions and Future Directions......Page 98
References......Page 100
About the Authors......Page 103
