Low Power Designs in Nanodevices and Circuits for Emerging Applications

Cover
Half Title
Title Page
Copyright Page
Table of Contents
Preface
About the Editors
List of Contributors
1 Low-power VLSI design using clock-gated technique
1.1 Introduction
1.1.1 Power consumption in VLSI digital circuits
1.1.2 Leakage power
1.1.3 Dynamic power lessening methodology
1.1.4 Procedure to decrease leakage power
1.2 Literature survey
1.3 Clock-gating methodology
1.4 Proposed clock-gated shift register
1.4.1 Low-power strategy
1.4.2 Influence of power dissipation
1.4.3 Reduction of temperature
1.4.4 Low-power design methodology
1.4.5 Power lessening via process technology
1.4.6 Power reduction through circuit/logic design
1.5 Results and discussion
1.6 Conclusion
References
2 Emerging applications and challenges in low-power device designs in flexible and stretchable low-power devices and strategies
2.1 Introduction
2.2 The need for low-power design
2.2.1 Clock gating
2.2.2 Power gating
2.2.3 Dynamic voltage and frequency scaling
2.2.4 Retention power gating
2.2.5 Save and restore power approach
2.3 Applications of low-power device design
2.4 Conclusion and future aspects
References
3 A highly stable, reliable ultralow-power design for 11T near-threshold FINFET SRAM
3.1 Introduction
3.2 The suggested WRE11T design: structure and working
3.2.1 Bitcell structure
3.2.2 Hold mode
3.2.3 Single-ended read operation with bitline precharging free
3.2.4 Write operation
3.3 Simulation setup, results, and analyses
3.3.1 Stabilities
3.3.2 Speed performance
3.3.3 Power analysis
3.3.4 Area comparison
3.4 Conclusion
References
4 Investigation and optimization of high stability 6T CNTFET SRAM cell with low power
4.1 Introduction: CNT and CN-FET
4.2 6T CN-SRAM cell structure and operation
4.2.1 Write mode
4.2.2 Read mode
4.2.3 Hold mode
4.3 Simulation results and discussion
4.4 Proposed method
4.5 Conclusion
References
5 Study of transistor sizing techniques for low-power design in FinFET technology
5.1 Introduction
5.2 Power optimization approaches
5.2.1 ONOFIC approach
5.2.2 LECTOR approach
5.3 Gate sizing procedures
5.3.1 Logical effort
5.3.2 EEC strategy
5.4 Flip-flop
5.4.1 TGFF scheme with logical effort approach
5.5 Simulations
5.5.1 Simulation results for power optimization methods
5.5.2 Simulation results for LE-based FF strategy
5.5.3 Simulation results of the EEC-based FF
5.5.4 Designing for maximum stability
5.5.5 Introducing power-delay-area and energy-delay-area space
5.5.6 Comparison of presented designs
5.6 Conclusion
References
6 Emerging nano devices for low-power applications: A research point of view
6.1 Introduction
6.1.1 CMOS inverter
6.1.2 Weak inversion
6.1.3 Designer’s approach
6.2 Nanoscale MOSFETs
6.2.1 Structure and operation of a MOSFET
6.2.2 Problems with nanoscale MOSFETs
6.3 Catalyst for low-power, low-voltage development
6.3.1 Industrial cross-fertilization
6.4 Carbon nanotube field effect transistors (CNTFET)
6.4.1 Basic physics of the carbon nanotube
6.4.2 Basics of CNTFETs
6.4.3 Fabrication
6.4.4 Performance comparison with other devices
6.4.5 Summary: CNTFET
6.5 Low-power market analysis
6.6 Conclusion
References
7 A review of the current research on graphene and its promising future
7.1 Introduction
7.2 Present and approaches
7.2.1 Graphene extracted from rice husks
7.2.2 Growth of epitaxial graphene
7.2.3 Saving on silicon carbide
7.2.4 An ethanol solution containing sodium and reduced hydrazine
7.2.5 Deposition of chemical vapors and colorant production
7.2.6 Adding graphene with lasers to colorant industrial components
7.2.7 Low graphene loading and nanocomposites
7.2.8 Translucent and supple conductive films made from graphene for screens and electrodes
7.2.9 Conductive inks for electronics that can be printed
7.2.10 Biomedical engineering
7.2.11 Microelectronics
7.2.12 Manufactured printing methods and equipment
7.2.13 Engineered textiles
7.2.14 Space
7.2.15 Encounters
7.2.16 Consensus and potential next steps
References
8 Analysis and optimization for low-power SRAM cells
8.1 Introduction
8.2 Memory array
8.3 Random access memory
8.4 Static random access memory
8.5 Dynamic random access memory
8.6 Conventional 6T SRAM cell
8.6.1 Modes of operation
8.7 Performance parameters of SRAM cells
8.7.1 SRAM power
8.7.2 Delay
8.7.3 Power delay product
8.7.4 Static noise margin
8.7.5 Power dissipation
8.7.6 Power consumption
8.7.7 Cell area
8.8 Power reduction techniques in SRAM cell
8.8.1 Multi-threshold CMOS (MTCMOS)
8.8.2 Dual threshold technique
8.8.3 Gated V[sub(DD)] technique
8.8.4 DRG (data retention gated ground) scheme
8.8.5 Self-controllable voltage level technique
8.8.6 Adaptive voltage level technique
8.8.7 Hybrid technique
8.8.8 Drowsy-cache technique
8.9 Conclusion
References
9 A comparative review on leakage power minimization techniques in SRAM
9.1 Introduction
9.2 History of SRAM
9.2.1 Write operation
9.2.2 Read operation
9.2.3 Hold operation
9.3 Sources of power dissipation in SRAM
9.4 Classification of leakage components
9.4.1 Sub-threshold leakage
9.4.2 Gate leakage
9.4.3 Junction leakage
9.5 Leakage reduction techniques in SRAM cell
9.5.1 Power-gating techniques
9.5.2 Biasing techniques
9.6 Comparison of various leakage power minimization techniques
9.7 Conclusion
References
10 Nonvolatile configurable logic block for FPGAs
10.1 Introduction
10.1.1 Field-programmable gate arrays
10.1.2 The logic block
10.1.3 Resistive random-access memory
10.2 Single-bit nonvolatile LUT
10.2.1 Circuit simulation
10.3 Multi-bit nonvolatile LUT
10.3.1 Multi-bit ReRAM LUT array
10.3.2 The MB LUT controller
10.3.3 WRITE operation
10.3.4 READ operation
10.3.5 Simulation results
10.4 Nonvolatile D flip-flop
10.4.1 Simulation results
10.5 The nonvolatile logic block
References
11 Efficient layout techniques to design physically realizable quantum-dot cellular automata circuits
11.1 Introduction
11.2 QCA fundamentals
11.2.1 Cell
11.2.2 Wire
11.2.3 Majority gate
11.2.4 Information flow and delay
11.2.5 Crossover
11.2.6 Fault tolerance
11.3 Clocking schemes in QCA
11.4 Layout techniques
11.4.1 Circuit segmentation
11.4.2 Placement of I/O cells
11.4.3 Crossovers
11.4.4 Layout approach
11.5 Multiplexer design
11.6 Conclusion
References
12 Low power reduction techniques for a 6T-SRAM cell design using CNTFET technology
12.1 Introduction
12.2 Literature work
12.3 Basic 6T SRAM cell design
12.3.1 Read operation
12.3.2 Write operation
12.4 Methods for reducing power leakage
12.4.1 Voltage divider technique
12.4.2 Power down transistor technique
12.5 Results and discussion
12.6 Conclusion
References
13 Design and development of integrated low power high performance MOSFET structure
13.1 Challenges due to leakage current in MOS transistor
13.2 Drawbacks of available leakage reduction techniques
13.3 Importance of area minimization of transistor
13.4 Process simplification and minimizing the cost of fabrication
13.5 Design and development of integrated low power high performance MOSFET structure
13.5.1 Minimization of reverse bias p-n junction leakage current and band to band tunneling leakage current
13.5.2 Minimization of subthreshold leakage current
13.5.3 Reduction of gate oxide tunneling leakage current
13.5.4 Reduction of leakage current due to hot carrier injection from bulk to SiO[sub(2)]
13.5.5 Reduction of gate induced drain leakage or GIDL
13.5.6 Reduction of channel punchthrough leakage current
13.5.7 Improvement of proposed structure
13.5.8 Reduction of area
13.5.9 Similar performance
13.6 Prototype
References
14 Low power designs for enhanced CMOS performance
14.1 Introduction
14.2 Sources leading to power dissipation
14.2.1 Dynamic power dissipation
14.2.2 Static/leakage power dissipation
14.2.3 Short-circuit power dissipation
14.3 Circuit-level implementation for power optimization
14.3.1 Static and dynamic logic
14.3.2 Voltage scaling and its issues
14.4 V[sub(th)] control techniques
14.4.1 MTCMOS
14.4.2 VTCMOS
14.4.3 DTCMOS
14.4.4 Dual-V(th)] CMOS
14.5 Dynamic logic desgn for power optimization
14.6 Comparative analysis
14.7 Conclusion
References
15 Recent advances in carbon nanotubes-based sensors
15.1 What is a sensor?
15.2 Characteristics of a good sensor
15.3 Carbon nanotube as a suitable material for sensor
15.4 Structure of CNTs
15.5 Limitation of CNT-based sensor
15.6 Methods to prepare polymer CNT composite
15.6.1 Melt mixing
15.6.2 In-situ polymerization
15.6.3 Mixing the solution
15.7 CNTs functionalization
15.8 CNT-based vapor sensor
15.9 CNT-based biosensors
15.9.1 CNT-based optical biosensors
15.9.2 Electrochemical CNT biosensors
15.9.3 Electrochemical immunosensors
15.10 CNT-based glucose sensor
15.11 CNT-based DNA sensor
References
16 Low power and low area multiplier and accumulator block for efficient implementation of FIR filter
16.1 Introduction
16.2 Reconfigurable devices configurations
16.3 Proposed optimized FIR filter
16.3.1 Proposed CSM multiplier block
16.3.2 Adder block diagram
16.4 Results and analysis
16.5 Conclusion
References
17 One-sided Schmitt-Trigger-based 10T SRAM cell with expanded read/write stabilities and less leakage power dissipation in 10-nm GNRFET technology
17.1 Introduction
17.2 The traditional 6T SRAM design: structure, limitations, and difficulties
17.3 Graphene nanoribbon field-effect transistor (GNRFET)
17.4 The suggested OSST10T design: structure and working
17.4.1 Bitcell structure
17.4.2 Hold mode
17.4.3 Single-ended read operation
17.4.4 Write operation with pseudo-differential structure
17.5 Simulation setup, results, and analyses
17.5.1 Stability
17.5.2 Speed performance
17.5.3 Leakage power dissipation
17.6 Conclusion
References
18 Advances in low-power devices: FinFETs, nanowire FETS, and CNT FET
18.1 Introduction to low-power devices
18.2 FinFETs
18.2.1 Introduction to FinFETs
18.2.2 Device physics mechanism
18.2.3 Fabrication steps
18.2.4 AC and DC characteristics
18.2.5 Issues and challenges
18.2.6 Applications
18.3 Carbon nanotubes
18.3.1 Fundamentals of carbon nanotubes
18.3.2 Types of CNTs
18.3.3 Properties of CNTs
18.3.4 CNT-based transistor
18.3.5 Applications
18.4 Nanowire FETs
18.4.1 Introduction
18.4.2 Device structure and its simulation
18.4.3 Device characteristics
18.4.4 Performance analysis
18.4.5 Applications of nanowire FETs
References
Index