The 19th Workshop on Languages and Compilers for Parallel Computing was heldinNovember2006inNewOrleans,LouisianaUSA.Morethan40researchers from around the world gathered together to present their latest results and to exchange ideas on topics ranging from parallel programming models, code generation,compilationtechniques,paralleldatastructureandparallelexecution models,toregisterallocationandmemorymanagementinparallelenvironments. Out of the 49 paper submissions, the Program Committee, with the help of external reviewers, selected 24 papers for presentation at the workshop. Each paper had at least three reviews and was extensively discussed in the comm- tee meeting. The papers were presented in 30-minute sessions at the workshop. One of the selected papers, while still included in the proceedings, was not p- sented because of an unfortunate visa problem that prevented the authors from attending the workshop. We werefortunateto havetwooutstanding keynoteaddressesatLCPC2006, both from UC Berkeley. Kathy Yelick presented “Compilation Techniques for Partitioned Global Address Space Languages.” In this keynote she discussed the issues in developing programming models for large-scale parallel machines and clusters, and how PGAS languages compare to languages emerging from the DARPA HPCS program.She also presented compiler analysis and optimi- tion techniques developed in the context of UPC and Titanium source-to-source compilers for parallel program and communication optimizations.
Author(s): Kathy Yelick (auth.), George Almási, Călin Caşcaval, Peng Wu (eds.)
Series: Lecture Notes in Computer Science 4382 : Theoretical Computer Science and General Issues
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2007
Language: English
Pages: 366
Tags: Programming Languages, Compilers, Interpreters; Programming Techniques; Computation by Abstract Devices; Computer Communication Networks; Arithmetic and Logic Structures; Data Structures
Front Matter....Pages -
Compilation Techniques for Partitioned Global Address Space Languages....Pages 1-1
Can Transactions Enhance Parallel Programs?....Pages 2-16
Design and Use of htalib – A Library for Hierarchically Tiled Arrays....Pages 17-32
SP@CE - An SP-Based Programming Model for Consumer Electronics Streaming Applications....Pages 33-48
Data Pipeline Optimization for Shared Memory Multiple-SIMD Architecture....Pages 49-63
Dependence-Based Code Generation for a CELL Processor....Pages 64-79
Expression and Loop Libraries for High-Performance Code Synthesis....Pages 80-95
Applying Code Specialization to FFT Libraries for Integral Parameters....Pages 96-110
A Characterization of Shared Data Access Patterns in UPC Programs....Pages 111-125
Exploiting Speculative Thread-Level Parallelism in Data Compression Applications....Pages 126-140
On Control Signals for Multi-Dimensional Time....Pages 141-155
The Berkeley View: A New Framework and a New Platform for Parallel Research....Pages 156-157
An Effective Heuristic for Simple Offset Assignment with Variable Coalescing....Pages 158-172
Iterative Compilation with Kernel Exploration....Pages 173-189
Quantifying Uncertainty in Points-To Relations....Pages 190-204
Cache Behavior Modelling for Codes Involving Banded Matrices....Pages 205-219
Tree-Traversal Orientation Analysis....Pages 220-234
UTS: An Unbalanced Tree Search Benchmark....Pages 235-250
Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files....Pages 251-266
Optimal Bitwise Register Allocation Using Integer Linear Programming....Pages 267-282
Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How....Pages 283-298
Custom Memory Allocation for Free....Pages 299-313
Optimizing the Use of Static Buffers for DMA on a CELL Chip....Pages 314-329
Runtime Address Space Computation for SDSM Systems....Pages 330-344
A Static Heap Analysis for Shape and Connectivity: Unified Memory Analysis: The Base Framework....Pages 345-363
Back Matter....Pages -
