This book constitutes the thoroughly refereed post-proceedings of the 18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005, held in Hawthorne, NY, USA in October 2005.
The 26 revised full papers and eight short papers presented were carefully selected during two rounds of reviewing and improvement. The papers are organized in topical sections on register optimization, compiling for FPGA's and network processors, model-driven and empirical optimization, parallel languages, speculative execution, run-time environments, high-productivity languages for HPC: compiler challenges, and compile-time analysis.
Author(s): Keith D. Cooper, Anshuman Dasgupta (auth.), Eduard Ayguadé, Gerald Baumgartner, J. Ramanujam, P. Sadayappan (eds.)
Series: Lecture Notes in Computer Science 4339 : Theoretical Computer Science and General Issues
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2006
Language: English
Pages: 480
Tags: Programming Languages, Compilers, Interpreters; Programming Techniques; Computation by Abstract Devices; Computer Communication Networks; Arithmetic and Logic Structures; Data Structures
Front Matter....Pages -
Revisiting Graph Coloring Register Allocation: A Study of the Chaitin-Briggs and Callahan-Koblenz Algorithms....Pages 1-16
Register Pressure in Software-Pipelined Loop Nests: Fast Computation and Impact on Architecture Design....Pages 17-31
Manipulating MAXLIVE for Spill-Free Register Allocation....Pages 32-46
Optimizing Packet Accesses for a Domain Specific Language on Network Processors....Pages 47-61
Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures....Pages 62-75
Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code....Pages 76-90
Applying Data Copy to Improve Memory Performance of General Array Computations....Pages 91-105
A Cache-Conscious Profitability Model for Empirical Tuning of Loop Fusion....Pages 106-120
Optimizing Matrix Multiplication with a Classifier Learning System....Pages 121-135
A Language for the Compact Representation of Multiple Program Versions....Pages 136-151
Efficient Computation of May-Happen-in-Parallel Information for Concurrent Java Programs....Pages 152-169
Evaluating the Impact of Thread Escape Analysis on a Memory Consistency Model-Aware Compiler....Pages 170-184
Concurrency Analysis for Parallel Programs with Textually Aligned Barriers....Pages 185-199
Titanium Performance and Potential: An NPB Experimental Study....Pages 200-214
Efficient Search-Space Pruning for Integrated Fusion and Tiling Transformations....Pages 215-229
Automatic Measurement of Instruction Cache Capacity....Pages 230-243
Combined ILP and Register Tiling: Analytical Model and Optimization Framework....Pages 244-258
Analytic Models and Empirical Search: A Hybrid Approach to Code Optimization....Pages 259-273
Testing Speculative Work in a Lazy/Eager Parallel Functional Language....Pages 274-288
Loop Selection for Thread-Level Speculation....Pages 289-303
Software Thread Level Speculation for the Java Language and Virtual Machine Environment....Pages 304-318
Lightweight Monitoring of the Progress of Remotely Executing Computations....Pages 319-333
Using Platform-Specific Performance Counters for Dynamic Compilation....Pages 334-346
A Domain-Specific Interpreter for Parallelizing a Large Mixed-Language Visualisation Application....Pages 347-361
Compiler Control Power Saving Scheme for Multi Core Processors....Pages 362-376
Code Transformations for One-Pass Analysis....Pages 377-396
Scalable Array SSA and Array Data Flow Analysis....Pages 397-412
Interprocedural Symbolic Range Propagation for Optimizing Compilers....Pages 413-424
Parallelization of Utility Programs Based on Behavior Phase Analysis....Pages 425-432
A Systematic Approach to Model-Guided Empirical Search for Memory Hierarchy Optimization....Pages 433-440
An Efficient Approach for Self-scheduling Parallel Loops on Multiprogrammed Parallel Computers....Pages 441-449
Dynamic Compilation for Reducing Energy Consumption of I/O-Intensive Applications....Pages 450-457
Supporting SELL for High-Performance Computing....Pages 458-465
Compiler Supports and Optimizations for PAC VLIW DSP Processors....Pages 466-474
Back Matter....Pages -
