We are pleased to present this collection of papers from the Second Workshop on Intelligent Memory Systems. Increasing die densities and inter chip communication costs continue to fuel interest in intelligent memory systems. Since the First Workshop on Mixing Logic and DRAM in 1997, technologies and systems for computation in memory have developed quickly. The focus of this workshop was to bring together researchers from academia and industry to discuss recent progress and future goals. The program committee selected 8 papers and 6 poster session abstracts from 29 submissions for inclusion in the workshop. Four to five members of the program committee reviewed each submission and their reviews were used to numerically rank them and guide the selection process. We believe that the resulting program is of the highest quality and interest possible. The selected papers cover a wide range of research topics such as circuit technology, processor and memory system architecture, compilers, operating systems, and applications. They also present a mix of mature projects, work in progress, and new research ideas. The workshop also included two invited talks. Dr. Subramanian Iyer (IBM Microelectronics) provided an overview of embedded memory technology and its potential. Dr. Mark Snir (IBM Research) presented the Blue Gene, an aggressive supercomputer system based on intelligent memory technology.
Author(s): Junji Ogawa, Mark Horowitz (auth.), Frederic T. Chong, Christoforos Kozyrakis, Mark Oskin (eds.)
Series: Lecture Notes in Computer Science 2107
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2001
Language: English
Pages: 200
Tags: Memory Structures; Computer Systems Organization and Communication Networks; Operating Systems; Logics and Meanings of Programs
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro....Pages 1-14
Software Controlled Reconfigurable On-chip Memory for High Performance Computing....Pages 15-32
Content-Based Prefetching: Initial Results....Pages 33-55
Memory System Support for Dynamic Cache Line Assembly....Pages 56-70
Adaptively Mapping Code in an Intelligent Memory Architecture....Pages 71-84
The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems⋆....Pages 85-103
Memory Management in a PIM-Based Architecture....Pages 104-121
Exploiting On-chip Memory Bandwidth in the VIRAM Compiler....Pages 122-134
FlexCache: A Framework for Flexible Compiler Generated Data Caching....Pages 135-146
Aggressive Memory-Aware Compilation....Pages 147-151
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips⋆....Pages 152-159
SAGE: A New Analysis and Optimization System for FlexRAM Architecture....Pages 160-168
Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems....Pages 169-178
The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems....Pages 179-182
Compiler-Directed Cache Line Size Adaptivity ⋆....Pages 183-187
Summary of Question/Answer Sessions for Workshop Presentations....Pages 188-191
