This book constitutes the refereed proceedings of the 10th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2000, held in Göttingen, Germany in September 2000.
The 33 revised full papers presented were carefully reviewed and selected for inclusion in the book. The papers are organized in sections on RTL power modeling, power estimation and optimization, system-level design, transistor level design, asynchronous circuit design, power efficient technologies, design of multimedia processing applications, adiabatic design and arithmetic modules, and analog-digital circuit modeling.
Author(s): Rene van Leuken, Reinder Nouta, Alexander de Graaf (auth.), Dimitrios Soudris, Peter Pirsch, Erich Barke (eds.)
Series: Lecture Notes in Computer Science 1918
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2000
Language: English
Pages: 338
Tags: Processor Architectures; Arithmetic and Logic Structures; Logic Design; System Performance and Evaluation; Systems and Information Theory in Engineering
Constraints, Hurdles and Opportunities for a Successful European Take-Up Action....Pages 1-2
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques....Pages 3-13
Power Models for Semi-autonomous RTL Macros....Pages 14-23
Power Macro-Modelling for Firm-Macro....Pages 24-35
RTL Estimation of Steering Logic Power....Pages 36-46
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers....Pages 47-55
Framework for High-Level Power Estimation of Signal Processing Architectures....Pages 56-65
Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses....Pages 66-75
Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions....Pages 76-87
A Holistic Approach to System Level Energy Optimization....Pages 88-107
Early Power Estimation for System-on-Chip Designs....Pages 108-117
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures....Pages 118-128
Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design....Pages 129-138
Impact of Voltage Scaling on Glitch Power Consumption....Pages 139-148
Degradation Delay Model Extension to CMOS Gates....Pages 149-158
Second Generation Delay Model for Submicron CMOS Process....Pages 159-167
Semi-modular Latch Chains for Asynchronous Circuit Design....Pages 168-177
Asynchronous First-in First-out Queues....Pages 178-186
Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance....Pages 187-194
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder....Pages 195-204
Low Power Design Techniques for Contactless Chipcards....Pages 205-206
Dynamic Memory Design for Low Data-Retention Power....Pages 207-216
Double-Latch Clocking Scheme for Low-Power I.P. Cores....Pages 217-224
Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip....Pages 225-232
Cost-Efficient C-Level Design of an MPEG-4 Video Decoder....Pages 233-242
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications....Pages 243-254
Design of Reversible Logic Circuits by Means of Control Gates....Pages 255-264
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates....Pages 265-275
An Adiabatic Multiplier....Pages 276-284
Logarithmic Number System for Low-Power Arithmetic....Pages 285-294
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits....Pages 295-305
PARCOURS — Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits....Pages 306-315
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits....Pages 316-326
Computer Aided Generation of Analytic Models for Nonlinear Function Blocks....Pages 327-335
