th Welcome to the proceedings of PATMOS 2007, the 17 in a series of international workshops. PATMOS 2007 was organized by Chalmers University of Technology with IEEE Sweden Chapter of the Solid-State Circuit Society technical - sponsorship and IEEE CEDA sponsorship. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2007 consisted of state-of-the-art te- nical contributions, three invited talks and an industrial session on design challenges in real-life projects. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on m- eling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert - viewers, selected the 55 papers presented at PATMOS. The papers were organized into 9 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.
Author(s): Lazaros Papadopoulos, Dimitrios Soudris (auth.), Nadine Azémard, Lars Svensson (eds.)
Series: Lecture Notes in Computer Science 4644 : Theoretical Computer Science and General Issues
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2007
Language: English
Pages: 586
Tags: Logic Design; Processor Architectures; System Performance and Evaluation; Arithmetic and Logic Structures; Memory Structures; Circuits and Systems
Front Matter....Pages -
System-Level Application-Specific NoC Design for Network and Multimedia Applications....Pages 1-9
Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements....Pages 10-19
A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms....Pages 20-30
An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture....Pages 31-42
Template Vertical Dictionary-Based Program Compression Scheme on the TTA....Pages 43-52
Asynchronous Functional Coupling for Low Power Sensor Network Processors....Pages 53-63
A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs....Pages 64-74
Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports....Pages 75-85
The Design and Implementation of a Power Efficient Embedded SRAM....Pages 86-96
Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN....Pages 97-106
Settling Time Minimization of Operational Amplifiers....Pages 107-116
Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs....Pages 117-124
Computation of Joint Timing Yield of Sequential Networks Considering Process Variations....Pages 125-137
A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation....Pages 138-147
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits....Pages 148-159
A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect....Pages 160-170
Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components....Pages 171-180
Logic Style Comparison for Ultra Low Power Operation in 65nm Technology....Pages 181-190
Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation....Pages 191-200
Clock Distribution Techniques for Low-EMI Design....Pages 201-210
Crosstalk Waveform Modeling Using Wave Fitting....Pages 211-221
Weakness Identification for Effective Repair of Power Distribution Network....Pages 222-231
New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses....Pages 232-241
On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects....Pages 242-254
Soft Error-Aware Power Optimization Using Gate Sizing....Pages 255-267
Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices....Pages 268-277
RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating....Pages 278-287
Functional Verification of Low Power Designs at RTL....Pages 288-299
XEEMU: An Improved XScale Power Simulator....Pages 300-309
Low Power Elliptic Curve Cryptography....Pages 310-319
Design and Test of Self-checking Asynchronous Control Circuit....Pages 320-329
An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips....Pages 330-339
Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA....Pages 340-351
Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform....Pages 352-362
The Energy Scalability of Wavelet-Based, Scalable Video Decoding....Pages 363-372
Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption....Pages 373-383
Exploiting Input Variations for Energy Reduction....Pages 384-393
A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates....Pages 394-403
Static Power Consumption in CMOS Gates Using Independent Bodies....Pages 404-412
Moderate Inversion: Highlights for Low Voltage Design....Pages 413-422
On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems....Pages 423-432
Semi Custom Design: A Case Study on SIMD Shufflers....Pages 433-442
Optimization for Real-Time Systems with Non-convex Power Versus Speed Models....Pages 443-452
Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS....Pages 453-462
A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits....Pages 463-473
Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates....Pages 474-484
A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning....Pages 485-494
Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems....Pages 495-504
Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate....Pages 505-515
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations....Pages 516-525
Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data....Pages 526-535
Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply....Pages 536-545
Low-Power Digital Filtering Based on the Logarithmic Number System....Pages 546-555
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling....Pages 556-565
Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers....Pages 566-575
Design and Industrialization Challenges of Memory Dominated SOCs....Pages 576-576
Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies....Pages 577-577
Analog Power Modelling....Pages 578-578
Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms....Pages 579-579
System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters....Pages 580-580
Back Matter....Pages -
