The new edition of this textbook is based on Dr. Thanh T. Tran’s 10+ years’ experience teaching high-speed digital and analog design courses at Rice University and 30+ years’ experience working in high-speed system design, including signal and power integrity in digital signal processing (DSP), computer, and embedded system. The book provides hands-on, practical instruction on high-speed digital and analog design for students and working engineers. The author first presents good high-speed digital and analog design practices that minimize both component and system noise and ensure system design success. He then presents guidelines to be used throughout the design process to reduce noise and radiation and to avoid common pitfalls while improving quality and reliability. The book is filled with tips on design and system simulation that minimize late stage redesign costs and product shipment delays. Hands-on design examples focusing on audio, video, analog filters, DDR memory, and power supplies are featured throughout. In addition, the author provides a practical approach to design multi-gigahertz high-speed serial busses (USB-C, PCIe, HDMI, DP) and simulate printed circuit board insertion and return loss using s-parameter models.
Author(s): Thanh T. Tran
Edition: 2
Publisher: Springer
Year: 2022
Language: English
Pages: 224
City: Cham
Preface
Acknowledgments
Contents
About the Author
Chapter 1: Challenges in High-Speed Systems Design
1.1 High-Speed Systems Overview
1.2 Challenges of Audio System
1.3 Challenges in Video System Design
1.4 Challenges in Communication System Design
1.5 Challenges of Computer System Design
1.6 Summary
References
Chapter 2: System Design Methodology
2.1 System Design Methodology
2.2 Pre-layout Analysis
2.3 PCB Layout
2.3.1 PCB Parasitics Extraction
2.4 Spice Simulation of Critical Circuits
2.5 Summary
References
Chapter 3: AC Versus DC
3.1 Alternating Current (AC) and Direct Current (DC)
3.2 Avoiding Pitfalls in AC-Coupled and DC-Couple Circuits
References
Chapter 4: Analog Filter Design
4.1 Anti-Aliasing Filters
4.1.1 Passive and Active Filters Characteristics
4.1.2 Passive Filter Design
4.1.2.1 First-Order Passive Lowpass Filter
4.1.2.2 Second-Order Passive Filter Design
4.1.3 Active Filter Design
4.1.3.1 Operational Amplifier (Op Amp) Fundamentals
Non-Inverting Amplifier
Inverting Amplifier
4.1.3.2 Biasing Op Amps
4.1.3.3 DC and AC-Coupled Op Amp Circuits
4.1.3.4 First Order Active Filter Design
4.1.3.5 Operational Amplifier (Op Amp) Fundamentals
Sallen-Key Circuit with Gain = 1
Sallen-Key Circuit with Gain = 2
Sallen-Key Circuit with Gain = 3 - 1/Q
4.2 Summary
References
Chapter 5: Data Converter Overview
5.1 CPU/DSP System
5.2 Analog-to-Digital Converter (ADC)
5.2.1 Sampling
5.2.2 Quantization Noise
5.2.3 ADC Digital Output Waveforms
5.3 Digital-to-Analog Converter (DAC)
5.4 Practical Data Converter Design Considerations
5.4.1 Resolution and Signal-to-Noise
5.4.2 Sampling Frequency
5.4.3 Input and Output Voltage Range
5.4.4 Differential Nonlinearity (DNL)
5.4.5 Integral Nonlinearity (INL)
5.5 Summary
References
Chapter 6: Transmission Line (TL) Effects
6.1 Transmission Line Theory
6.2 Parallel Termination Simulations
6.3 Practical Considerations of TL
6.4 Simulations and Experimental Results of TL
6.4.1 TL Without Load or Source Termination
6.4.2 TL with Series Source Termination
6.5 Ground Grid Effects on TL
6.6 Minimizing TL Effects
References
Chapter 7: Transmission Line (TL) Effects in Frequency Domain
7.1 S-Parameter Fundamentals
7.2 Minimizing TL Effects in Frequency Domain
References
Chapter 8: Effects of Crosstalk
8.1 Current Return Paths
8.2 Crosstalk Caused by Radiation
8.3 Summary
References
Chapter 9: Memory Sub-system Design Considerations
9.1 DDR Memory Overview
9.1.1 DDR Write Cycle
9.1.2 DDR Read Cycle
9.2 DDR Memory Signal Integrity
References
Chapter 10: USB 3.1 Channel Design
10.1 USB 3.1 10 Gbps Channel Design
10.2 Layout Considerations of USB 3.1 10 Gbps Channels
10.3 USB 3.1 10 Gbps Channel Design
References
Chapter 11: Phase-Locked Loop (PLL)
11.1 Analog PLL (APLL)
11.2 PLL Jitter
11.2.1 Long-Term Jitter
11.2.2 Cycle-to-Cycle Jitter
11.2.2.1 Cycle-to-Cycle Jitter Measurement
11.2.3 Period Jitter
11.2.3.1 Period Jitter Measurement
11.3 Digital PLL (DPLL)
11.4 APLL and DPLL Jitter Characterization
11.5 PLL Noise Isolation Techniques
11.5.1 Pi and T Filters
11.5.2 Linear Voltage Regulators
11.6 Summary
References
Chapter 12: Power Supply Design Considerations
12.1 Power Supply Architectures
12.2 System Power Supply Architectural Considerations
12.2.1 CORE Voltage Regulator Design
12.2.2 IO Voltage Regulator Design
12.3 Power Sequencing Considerations
12.4 Summary
References
Chapter 13: Power Integrity
13.1 Power Supply Decoupling Techniques
13.1.1 Capacitor Characteristics
13.1.2 Inductor Characteristics
13.1.3 Ferrite Bead Characteristics
13.1.4 General Rule-of-Thumb Decoupling Method
13.1.5 Analytical Method of Decoupling
13.1.5.1 Core Voltage Decoupling Steps
13.1.5.2 IO Voltage Decoupling Steps
Region 4
13.1.6 Target Impedance Method of Decoupling
13.1.7 Placing Decoupling Capacitors
13.2 High-Frequency Noise Isolation
13.2.1 Pi Filter Design
13.2.1.1 Pi Filter Design Example
13.2.2 T Filter Design
13.2.2.1 T Filter Design Example
13.3 Summary
References
Chapter 14: Printed Circuit Board (PCB) Layout
14.1 Printed Circuit Board (PCB) Stackup
14.2 Microstrip and Stripline
14.3 PCB Traces and Vias
14.3.1 PCB Trace Inductance
14.3.2 PCB Trace Impedance
14.3.3 Vias
14.4 Image Plane
14.5 PCB Routing Guidelines
14.6 Summary
References
Chapter 15: Electromagnetic Interference (EMI)
15.1 FCC Part 15 B Overview
15.2 EMI Fundamentals
15.3 Digital Signals
15.4 Current Loops
15.5 Power Supply
15.6 Transmission Line
15.7 Power and Ground Planes
15.8 Summary: EMI Reduction Guidelines
References
Index
