This book constitutes the refereed proceedings of the Second International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2007, held in Ghent, Belgium, in January 2007.
The 19 revised full papers presented together with one invited keynote paper were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections on secure and low-power embedded memory systems, architecture/compiler optimizations for efficient embedded processing, adaptive microarchitectures, architecture evaluation techniques, generation of efficient embedded applications, as well as optimizations and architectural tradeoffs for embedded systems.
Author(s): Thomas M. Conte (auth.), Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer (eds.)
Series: Lecture Notes in Computer Science 4367 : Theoretical Computer Science and General Issues
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2007
Language: English
Pages: 307
Tags: Arithmetic and Logic Structures; Processor Architectures; Input/Output and Data Communications; Logic Design; Computer Communication Networks; Programming Languages, Compilers, Interpreters
Front Matter....Pages -
Front Matter....Pages 1-1
Keynote: Insight, Not (Random) Numbers: An Embedded Perspective....Pages 3-3
Front Matter....Pages 5-5
Compiler-Assisted Memory Encryption for Embedded Processors....Pages 7-22
Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems....Pages 23-37
Applying Decay to Reduce Dynamic Power in Set-Associative Caches....Pages 38-53
Front Matter....Pages 55-55
Virtual Registers: Reducing Register Pressure Without Enlarging the Register File....Pages 57-70
Bounds Checking with Taint-Based Analysis....Pages 71-86
Reducing Exit Stub Memory Consumption in Code Caches....Pages 87-101
Front Matter....Pages 103-103
Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling....Pages 105-119
Fetch Gating Control Through Speculative Instruction Window Weighting....Pages 120-135
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches....Pages 136-150
Branch History Matching: Branch Predictor Warmup for Sampled Simulation....Pages 153-167
Sunflower : Full-System, Embedded Microarchitecture Evaluation....Pages 168-182
Efficient Program Power Behavior Characterization....Pages 183-197
Front Matter....Pages 199-199
Performance/Energy Optimization of DSP Transforms on the XScale Processor....Pages 201-214
Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms....Pages 215-226
A Throughput-Driven Task Creation and Mapping for Network Processors....Pages 227-241
Front Matter....Pages 243-243
MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization....Pages 245-260
Evaluation of Offset Assignment Heuristics....Pages 261-275
Customizing the Datapath and ISA of Soft VLIW Processors....Pages 276-290
Instruction Set Extension Generation with Considering Physical Constraints....Pages 291-305
Back Matter....Pages -
