This book constitutes the refereed proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010.
The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were carefully reviewed and selected from 94 submissions. The papers are organized in topical sections on architectural support for concurrency; compilation and runtime systems; reconfigurable and customized architectures; multicore efficiency, reliability, and power; memory organization and optimization; and programming and analysis of accelerators.
Author(s): Bob Iannucci (auth.), Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell (eds.)
Series: Lecture Notes in Computer Science 5952 : Theoretical Computer Science and General Issues
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2010
Language: English
Pages: 370
Tags: Arithmetic and Logic Structures; Processor Architectures; Input/Output and Data Communications; Logic Design; Computer Communication Networks; Programming Languages, Compilers, Interpreters
Front Matter....Pages -
Embedded Systems as Datacenters....Pages 1-1
Larrabee: A Many-Core Intel Architecture for Visual Computing....Pages 2-2
Remote Store Programming....Pages 3-17
Low-Overhead, High-Speed Multi-core Barrier Synchronization....Pages 18-34
Improving Performance by Reducing Aborts in Hardware Transactional Memory....Pages 35-49
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems....Pages 50-65
Split Register Allocation: Linear Complexity Without the Performance Penalty....Pages 66-80
Trace-Based Data Layout Optimizations for Multi-core Processors....Pages 81-95
Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors....Pages 96-110
Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures....Pages 111-125
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions....Pages 126-140
Accelerating XML Query Matching through Custom Stack Generation on FPGAs....Pages 141-155
An Application-Aware Load Balancing Strategy for Network Processors....Pages 156-170
Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays....Pages 171-185
Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors....Pages 186-200
Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors....Pages 201-215
RELOCATE: Re gister File Loc al A ccess Pat te rn Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor....Pages 216-231
Performance and Power Aware CMP Thread Allocation Modeling....Pages 232-246
Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching....Pages 247-261
Scalable Shared-Cache Management by Containing Thrashing Workloads....Pages 262-276
SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs....Pages 277-291
DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems....Pages 292-306
Tagged Procedure Calls ( TPC ): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor....Pages 307-321
Analysis of Task Offloading for Accelerators....Pages 322-336
Offload – Automating Code Migration to Heterogeneous Multicore Systems....Pages 337-352
Computer Generation of Efficient Software Viterbi Decoders....Pages 353-368
Back Matter....Pages -
