As Chairmen of HiPEAC 2005, we have the pleasure of welcoming you to the proceedings of the ?rst international conference promoted by the HiPEAC N- work of Excellence. During the last year, HiPEAC has been building its clusters of researchers in computer architecture and advanced compiler techniques for embedded and high-performance computers. Recently, the Summer School has been the seed for a fruitful collaboration of renowned international faculty and young researchers from 23 countries with fresh new ideas. Now, the conference promises to be among the premier forums for discussion and debate on these research topics. Theprestigeofasymposiumismainlydeterminedbythequalityofitstech- cal program. This ?rst programlived up to our high expectations, thanks to the largenumber of strong submissions. The ProgramCommittee received a total of 84 submissions; only 17 were selected for presentation as full-length papers and another one as an invited paper. Each paper was rigorously reviewed by three ProgramCommittee members and at least one external referee. Many reviewers spent a great amount of e?ort to provide detailed feedback. In many cases, such feedback along with constructive shepherding resulted in dramatic improvement in the quality of accepted papers. The names of the Program Committee m- bers and the referees are listed in the proceedings. The net result of this team e?ort is that the symposium proceedings include outstanding contributions by authors from nine countries in three continents. In addition to paper presentations, this ?rst HiPEAC conference featured two keynotes delivered by prominent researchers from industry and academia.
Author(s): Markus Levy (auth.), Tom Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer (eds.)
Series: Lecture Notes in Computer Science 3793 : Theoretical Computer Science and General Issues
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2005
Language: English
Pages: 318
Tags: Arithmetic and Logic Structures; Input/Output and Data Communications; Logic Design; Processor Architectures; Computer Communication Networks; Programming Languages, Compilers, Interpreters
Front Matter....Pages -
Front Matter....Pages 1-1
Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications....Pages 3-4
Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges....Pages 5-5
Software Defined Radio – A High Performance Embedded Challenge....Pages 6-26
Front Matter....Pages 27-27
A Practical Method for Quickly Evaluating Program Optimizations....Pages 29-46
Efficient Sampling Startup for Sampled Processor Simulation....Pages 47-67
Enhancing Network Processor Simulation Speed with Statistical Input Sampling....Pages 68-83
Front Matter....Pages 85-85
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems....Pages 87-101
Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation....Pages 102-115
Streaming Sparse Matrix Compression/Decompression....Pages 116-129
XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs....Pages 130-149
Front Matter....Pages 151-151
Memory-Centric Security Architecture....Pages 153-168
A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management....Pages 169-183
Arc3D: A 3D Obfuscation Architecture....Pages 184-199
Front Matter....Pages 201-201
Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations....Pages 203-217
Induction Variable Analysis with Delayed Abstractions....Pages 218-232
Garbage Collection Hints....Pages 233-248
Front Matter....Pages 249-249
Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors....Pages 251-265
Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture....Pages 266-285
A Single (Unified) Shader GPU Microarchitecture for Embedded Systems....Pages 286-301
A Low-Power DSP-Enhanced 32-Bit EISC Processor....Pages 302-316
Back Matter....Pages -
