This book introduces power amplifier design in 22nm FDSOI CMOS dedicated towards 5G applications at 28 GHz and presents 4 state-of-the-art power amplifier designs. The authors discuss power amplifier performance metrics, design trade-offs, and presents different power amplifier classes utilizing efficiency enhancement techniques at 28 GHz. The book presents the design process from theory, simulation, layout, and finally measurement results.
Author(s): Nourhan Elsayed, Hani Saleh, Baker Mohammad, Mohammed Ismail, Mihai Sanduleanu
Series: Analog Circuits and Signal Processing
Publisher: Springer
Year: 2022
Language: English
Pages: 110
City: Cham
Preface
Acknowledgments
Contents
Acronyms
1 Introduction
1.1 Motivation for High Efficiency Power Amplifiers for5G Technology
1.2 Book Organization
References
2 Power Amplifier Fundamentals
2.1 Performance Metrics
2.1.1 Power Amplifiers Efficiency
2.1.2 Output Power Capability
2.1.3 Linearity
2.1.3.1 1-dB Compression Point
2.1.3.2 Third Order Intercept Point (IP3)
2.1.4 Figure of Merit (FoM)
2.2 Power Amplifier Classes
2.2.1 Linear Power Amplifiers (A, A/B, B, and C)
2.2.2 Switched Mode Power Amplifiers (SMPAs)
2.2.3 Summary
2.3 Efficiency Enhancement Techniques
2.3.1 Dynamic Biasing
2.3.2 Envelope Tracking
2.3.3 Doherty Configuration
2.4 Technology Limitations
2.4.1 Low Breakdown Voltages
2.4.2 Low Transconductance
2.4.3 Low fT and fmax
2.5 Cascoding for Larger Power
References
3 Doherty Power Amplifier
3.1 Doherty Power Amplifier Design
3.1.1 Transistor Sizing
3.1.2 Design of Quarter Wavelength Transmission Line
3.1.3 Doherty Power Amplifier Integration
3.2 Simulation and Measurements
3.3 Summary
References
4 Delayed Switched Cascode Class-E Amplifier
4.1 Doherty Power Amplifier Design and Architecture
4.1.1 Classical Class-E
4.1.2 Cascode Class-E
4.1.3 Switched Cascode Class-E with Tunable Transmission Line
4.2 Implementation and Measurement Results
4.2.1 Small Signal Measurements
4.2.2 Large Signal Measurements
4.2.3 Comparison with the State-of-the-Art Class-E and Cascode PAs
4.3 Summary
References
5 Delayed Switched Cascode Doherty Class-E PA
5.1 Proposed Class-E Doherty PA Design
5.1.1 Active Balun
5.1.2 VGA
5.1.3 Integration of Class-E Doherty PA
5.2 Simulation and Measurement
5.2.1 Small Signal Parameters
5.2.2 Large Signal Measurements
5.2.3 Comparison with State of the Art
5.3 Summary
References
6 A 28 GHz Inverse Class-D Power Amplifier
6.1 Conventional CMCD PA
6.2 Proposed CMCD Topology
6.3 Measurements Results
6.3.1 Comparison with State-of-the-Art CMCD PAs
6.4 Summary
References
7 Phased-Array Transmitter
7.1 Conventional Direct Conversion Transmitter Architecture
7.2 Proposed Phased-Array Transmitter Architecture
7.3 LO Quadrature Generation
7.4 Tunable Low Pass Filter
7.5 Low Frequency VGA
7.6 Power Divider Design
7.6.1 Noise Analysis for Power Divider
7.6.2 Simulations and Measurement Results
7.6.3 Comparison with State of the Art
7.7 Simulation Results
7.8 Summary
References
Index
