This book provides an overview of current hardware security primitives, their design considerations, and applications. The authors provide a comprehensive introduction to a broad spectrum (digital and analog) of hardware security primitives and their applications for securing modern devices. Readers will be enabled to understand the various methods for exploiting intrinsic manufacturing and temporal variations in silicon devices to create strong security primitives and solutions. This book will benefit SoC designers and researchers in designing secure, reliable, and trustworthy hardware.- Provides guidance and security engineers for protecting their hardware designs;
- Covers a variety digital and analog hardware security primitives and applications for securing modern devices;
- Helps readers understand PUF, TRNGs, silicon odometer, and cryptographic hardware design for system security.
Author(s): Mark Tehranipoor, Nitin Pundir, Nidish Vashistha, Farimah Farahmandi
Publisher: Springer
Year: 2022
Language: English
Pages: 355
City: Cham
Preface
Acknowledgments
Contents
1 Intrinsic Racetrack PUF
1.1 Introduction
1.2 Background
1.2.1 PUF Performance Metrics
1.3 Racetrack PUF
1.3.1 Arbiter PUF
1.3.2 Ring-Oscillator PUF
1.3.3 ClockPUF
1.3.4 Advancement in Classical PUF
1.4 Conclusions
References
2 Intrinsic-Transient PUF
2.1 Introduction
2.2 Background
2.3 Design Strategy and Applications
2.3.1 PUF Design for FPGA-Based Embedded Systems
2.3.2 Transient Effect Ring Oscillator-Based PUF
2.3.3 Glitch PUF
2.3.4 TERO-PUF on SRAM FPGAs
2.3.5 TERO-PUF in IoTs
2.4 Conclusions
References
3 Direct Intrinsic Characterization PUF
3.1 Introduction
3.2 Cellular Neural Network PUF
3.3 Power Distribution PUF
3.4 QUALPUF
3.5 Via-PUF
3.6 Threshold Voltage PUF
3.6.1 Conclusions
References
4 Volatile Memory-Based PUF
4.1 Introduction
4.2 Background
4.2.1 PUF Performance Evaluation Metrics
4.3 Comparative Analysis of Volatile Memory-Based PUF
4.3.1 Bistable Ring PUF
4.3.2 DRAM-Based Intrinsic PUF
4.3.3 MECCA PUF
4.3.4 Intrinsic Rowhammer PUF
4.3.5 SRAM Random Address Error-Based Chip ID Generation
4.4 Conclusions
References
5 Extrinsic Direct Characterization PUF
5.1 Introduction
5.2 Background
5.2.1 PUF Preliminaries
5.2.2 Challenges of Direct Extrinsic Characterization
5.3 Extrinsic Direct Characterization PUF
5.3.1 ALILE Diode-Based PUF
5.3.2 Nano-Electro-Mechanical-Based PUF
5.3.3 Carbon Nanotube-Based PUF
5.3.4 MEMs Accelerometer Sensor-Based PUF
5.3.5 Capacitor-Based PUF
5.4 Conclusions
References
6 Hybrid Extrinsic Radio Frequency PUF
6.1 Introduction
6.2 Background
6.2.1 Threat Model
6.2.2 Challenges
6.3 Radio PUF in IoT Security
6.4 PUF-Embedded RFID
6.5 RFID Tags as Certificates of Authenticity
6.6 PUF in Ambient World
6.7 Radio Frequency-DNA
6.8 Conclusions
References
7 Optical PUF
7.1 Introduction
7.2 Background
7.2.1 Threat Model
7.2.2 Challenges
7.3 CD Fingerprint as Optical PUF
7.3.1 Fingerprint Extraction
7.3.2 Entropy Estimation
7.3.3 Robustness
7.3.4 Limitations
7.4 Counterfeit Deterrent Currency
7.4.1 Diffraction-Based Hologram
7.4.2 Proof of Authenticity
7.4.3 Limitations
7.5 Anti-counterfeit Nanowire Fingerprint
7.5.1 Fingerprint Extraction
7.6 Authentication
7.6.1 Limitations
7.7 Anti-counterfeit Plasmonic Nanoparticles
7.7.1 Fingerprint Generation
7.7.2 Limitations
7.8 Anti-counterfeit Random Pattern
7.8.1 Bit Extraction and ECC Encoding/Decoding
7.8.2 Limitations
7.9 Anti-counterfeit Liquid Crystal Shell
7.9.1 Security Framework Model
7.9.2 Security Argumentation and Limitation
7.9.3 Application in Object Identification and Advantages
7.10 FiberID: Molecular Level Identification
7.10.1 Operating Principle
7.10.2 FiberID System
7.10.2.1 Challenges and Limitations
7.11 Conclusions
References
8 True Random Number Generators
8.1 Introduction
8.2 Background
8.3 TRNG Architectures
8.3.1 Technology Independent TRNG
8.3.2 Embedded TRNG with Self-Testing Capability
8.3.3 FPGA Vendor Independent TRNG Design
8.3.4 High-Speed TRNG-Based on Open-Loop Structures
8.3.5 FPGA-Based Compact TRNG
8.3.6 Meta-Stability-Based TRNG
8.3.7 TRNG Resistant to Active Attacks
8.4 Conclusions
References
9 Hardware Security Primitives Based on Emerging Technologies
9.1 Introduction
9.2 Background
9.2.1 Emerging Devices
9.2.2 Security Applications of Emerging Devices
9.3 Emerging Technologies in Hardware Security
9.3.1 Security Beyond CMOS
9.3.2 DRAM-Based Security Primitives
9.3.3 Security Beyond PUF Using Emerging Technologies
9.3.4 Emerging Transistor Technologies for Hardware Security
9.3.5 SiNW and Graphene SymFET-Based Hardware Security Primitive
9.3.6 Polymorphic and Stochastic Spin Hall Effect Devices
9.4 Future Research Directions
9.5 Conclusions
References
10 Hardware Camouflaging in Integrated Circuits
10.1 Introduction
10.2 Background
10.3 CamoPerturb
10.4 Covert Gates—IC Protection Method Using Undetectable Camouflaging
10.5 Logic Locking and IC Camouflaging Schemes
10.6 Security Analysis of IC Camouflaging
10.7 Conclusions
References
11 Embedded Watermarks
11.1 Introduction
11.2 Background
11.3 Hardware IP Security
11.3.1 Watermark Insertion Process and Requirements
11.3.1.1 Additional Functionality
11.3.1.2 Additional Constraint
11.3.2 Watermark Extraction
11.4 FLATS: FPGA Authentication and Tamper Detection
11.4.1 Novelty of FLATS
11.4.2 Methodology
11.4.3 Experimentation
11.4.4 Limitations
11.5 Side-Channel-Based Watermarks
11.5.1 Methodology
11.5.2 Attack Scenarios
11.5.3 Experimentation
11.6 Embedded Watermarking for Hardware Trojan Detection
11.6.1 Methodology
11.6.2 Experimentation
11.6.3 Strength and Weakness
11.7 Enabling IP and IC Forward Trust
11.7.1 Related Works and Novelty
11.7.2 Methodology
11.7.3 Experimentation
11.7.4 Strength and Limitations
11.8 Conclusions
References
12 Lightweight Cryptography
12.1 Introduction
12.2 Background
12.2.1 Characteristics of Lightweight Cryptography
12.2.2 Lightweight Cryptography's Design Considerations
12.3 Lightweight Cryptographic Primitives
12.3.1 Lightweight Block Ciphers
12.3.2 Lightweight Stream Ciphers
12.3.3 Lightweight Hash Functions
12.3.4 Lightweight Message Authentication Codes
12.4 Standard for Lightweight Cryptography
12.5 Lightweight Ciphers for IoT Devices
12.6 CHACHA20-Poly1305 Authenticated Encryption
12.7 Conclusions
References
13 Virtual Proof of Reality
13.1 Introduction
13.2 Background
13.3 Illustrative Overview of Virtual Proof of Reality
13.3.1 Physical Implementation of Virtual Proof of Reality
13.3.2 Keyless Cryptographic Security Primitive
13.3.3 Smart Contract Privacy Protection: AI in Cyber Systems
13.3.4 Secure Key Exchange Protocol
13.3.5 Secure Wireless Sensing
13.4 Conclusions
References
14 Analog Security
14.1 Introduction
14.2 Background
14.3 Stochastic All-Digital Weak PUF for AMS Circuits
14.4 Chaogate
14.5 Key-Based Parameter Obfuscation
14.6 Combinational Locking
14.7 Obfuscation with Analog Neural Network
14.8 Multi-threshold Design
14.9 Conclusions
References
15 Tamper Detection
15.1 Introduction
15.2 Background
15.2.1 Threat Model
15.2.2 Challenges in Tamper Detection
15.3 Various Tamper Prevention and Detection Mechanisms
15.3.1 FLATS
15.3.2 Recycled IC Detection
15.3.3 Digital-Oscillator-Based Sensor for EM Probing Detection
15.3.4 Tamper Detection Using a Temperature-Sensitive Circuit
15.3.5 Advanced Tamper Detection Using a Conductive Mesh
15.4 Conclusions
References
16 Counterfeit and Recycled IC Detection
16.1 Introduction
16.2 Background
16.3 Recycled and Counterfeit IC Detection
16.3.1 IC Fingerprinting Using Lightweight On-chip Sensor
16.3.1.1 RO-Based Sensor
16.3.1.2 Anti-fuse (AF)-Based Sensor
16.3.2 NBTI-Aware CDIR Sensor
16.3.3 IC Tracing in Supply Chain
16.3.4 Thwarting Counterfeit IC Using Blockchain
16.3.4.1 eChain Architecture
16.3.4.2 IC Supply Chain Transactions
16.3.4.3 IC Verification Using eChain
16.4 Conclusions
References
17 Package-Level Counterfeit Detection and Avoidance
17.1 Introduction
17.2 Background
17.3 Counterfeit Detection and Avoidance
17.3.1 Methods and Challenges for Counterfeit Detection
17.3.2 Methods and Challenges for Counterfeit Avoidance
17.3.3 Counterfeit PCB Detection
17.3.4 DNA Marking and Authentication
17.3.5 Advanced Anti-counterfeiting Applications
17.4 Conclusions
References
18 Side-Channel Protection in Cryptographic Hardware
18.1 Introduction
18.2 Background
18.3 Threat Model
18.4 A Compact Threshold Implementation of AES
18.5 Efficient AES Threshold Implementation
18.6 Masking Based on Secret Sharing, Threshold Cryptography, and Multi-party Computation Protocols
18.7 Provably Secure AES Randomization Technique
18.8 Conclusions
References
19 Fault Injection Resistant Cryptographic Hardware
19.1 Introduction
19.2 Background
19.3 Fault Injection Countermeasures
19.4 Algebraic Fault Analysis
19.5 Double Data Rate AES Architecture
19.6 Randomness in Fault Attack Countermeasures
19.7 Duplicated and Complemented Paths for Side-Channel and Fault Resistance
19.8 Conclusions
References
Index
