Updated with modern coverage, a streamlined presentation, and excellent companion software, this seventh edition of FUNDAMENTALS OF LOGIC DESIGN achieves yet again an unmatched balance between theory and application. Authors Charles H. Roth, Jr. and Larry L. Kinney carefully present the theory that is necessary for understanding the fundamental concepts of logic design while not overwhelming students with the mathematics of switching theory. Divided into 20 easy-to-grasp study units, the book covers such fundamental concepts as Boolean algebra, logic gates design, flip-flops, and state machines. By combining flip-flops with networks of logic gates, students will learn to design counters, adders, sequence detectors, and simple digital systems. After covering the basics, this text presents modern design techniques using programmable logic devices and the VHDL hardware description language.
Author(s): Charles H. Roth, Larry L. Kinney
Edition: 7
Publisher: Cengage Learning
Year: 2013
Language: English
Pages: 816
Tags: Информатика и вычислительная техника;Искусственный интеллект;
Cover
......Page 1
Title Page
......Page 2
Copyright
......Page 3
Brief Contents......Page 5
Contents......Page 7
Preface......Page 15
How to Use This Book for Self-Study......Page 20
About the Authors......Page 21
Objectives......Page 23
Study Guide......Page 24
1.1: Digital Systems and Switching Circuits......Page 28
1.2: Number Systems and Conversion......Page 30
1.3: Binary Arithmetic......Page 34
1.4: Representation of Negative Numbers......Page 38
1.5: Binary Codes......Page 43
Problems......Page 46
Objectives......Page 51
Study Guide......Page 52
2.1: Introduction......Page 58
2.2: Basic Operations......Page 59
2.3: Boolean Expressions and Truth Tables......Page 61
2.4: Basic Theorems......Page 63
2.5: Commutative, Associative, Distributive, and DeMorgan's Laws......Page 65
2.6: Simplification Theorems......Page 68
2.7: Multiplying out and Factoring......Page 71
2.8: Complementing Boolean Expressions......Page 74
Problems......Page 75
Objectives......Page 82
Study Guide......Page 83
3.1: Multiplying out and Factoring Expressions......Page 88
3.2: Exclusive-OR and Equivalence Operations......Page 90
3.3: The Consensus Theorem......Page 92
3.4: Algebraic Simplification of Switching Expressions......Page 94
3.5: Proving Validity of an Equation......Page 96
Programmed Exercise 3.2......Page 99
Programmed Exercise 3.3......Page 100
Programmed Exercise 3.4......Page 101
Programmed Exercise 3.5......Page 103
Problems......Page 104
Objectives......Page 109
Study Guide......Page 110
4.1: Conversion of English Sentences to Boolean Equations......Page 116
4.2: Combinational Logic Design Using a Truth Table......Page 118
4.3: Minterm and Maxterm Expansions......Page 119
4.4: General Minterm and Maxterm Expansions......Page 122
4.5: Incompletely Specified Functions......Page 125
4.6: Examples of Truth Table Construction......Page 126
4.7: Design of Binary Adders and Subtracters......Page 130
Problems......Page 136
Objectives......Page 145
Study Guide......Page 146
5.1: Minimum Forms of Switching Functions......Page 156
5.2: Two- and Three-Variable Karnaugh Maps......Page 158
5.3: Four-Variable Karnaugh Maps......Page 163
5.4: Determination of Minimum Expressions Using Essential Prime Implicants......Page 166
5.5: Five-Variable Karnaugh Maps......Page 171
5.6: Other Uses of Karnaugh Maps......Page 174
5.7: Other Forms of Karnaugh Maps......Page 175
Programmed Exercise 5.1......Page 176
Programmed Exercise 5.2......Page 178
Problems......Page 181
Objectives......Page 189
Study Guide......Page 190
6.1: Determination of Prime Implicants......Page 195
6.2: The Prime Implicant Chart......Page 198
6.3: Petrick's Method......Page 201
6.4: Simplification of Incompletely Specified Functions......Page 203
6.5: Simplification Using Map-Entered Variables......Page 204
6.6: Conclusion......Page 206
Programmed Exercise 6.1......Page 207
Problems......Page 211
Objectives......Page 215
Study Guide......Page 216
7.1: Multi-Level Gate Circuits......Page 221
7.2: NAND and NOR Gates......Page 226
7.3: Design of Two-Level NAND- and NOR-Gate Circuits......Page 228
7.4: Design of Multi-Level NAND- and NOR-Gate Circuits......Page 231
7.5: Circuit Conversion Using Alternative Gate Symbols......Page 232
7.6: Design of Two-Level, Multiple-Output Circuits......Page 236
7.7: Multiple-Output NAND- and NOR-Gate Circuits......Page 239
Problems......Page 240
Objectives......Page 247
Study Guide......Page 248
8.1: Review of Combinational Circuit Design......Page 251
8.2: Design of Circuits with Limited Gate Fan-In......Page 252
8.3: Gate Delays and Timing Diagrams......Page 254
8.4: Hazards in Combinational Logic......Page 256
8.5: Simulation and Testing of Logic Circuits......Page 262
Problems......Page 265
Objectives......Page 274
Study Guide......Page 275
9.1: Introduction......Page 282
9.2: Multiplexers......Page 283
9.3: Three-State Buffers......Page 287
9.4: Decoders and Encoders......Page 290
9.5: Read-Only Memories......Page 293
9.6: Programmable Logic Devices......Page 297
9.7: Complex Programmable Logic Devices......Page 302
9.8: Field-Programmable Gate Arrays......Page 304
Problems......Page 308
Objectives......Page 316
Study Guide......Page 317
10.1: VHDL Description of Combinational Circuits......Page 321
10.2: VHDL Models for Multiplexers......Page 326
10.3: VHDL Modules......Page 328
10.4: Signals and Constants......Page 333
10.5: Arrays......Page 334
10.6: VHDL Operators......Page 337
10.7: Packages and Libraries......Page 338
10.8: IEEE Standard Logic......Page 340
10.9: Compilation and Simulation of VHDL Code......Page 343
Problems......Page 344
Design Problems......Page 349
Objectives......Page 353
Study Guide......Page 354
11.1: Introduction......Page 358
11.2: Set-Reset Latch......Page 360
11.3: Gated Latches......Page 364
11.4: Edge-Triggered D Flip-Flop......Page 368
11.5: S-R Flip-Flop......Page 371
11.6: J-K Flip-Flop......Page 372
11.7: T Flip-Flop......Page 373
11.8: Flip-Flops with Additional Inputs......Page 374
11.9: Asynchronous Sequential Circuits......Page 376
11.10: Summary......Page 379
Problems......Page 380
Programmed Exercise 11.35......Page 389
Objectives......Page 392
Study Guide......Page 393
12.1: Registers and Register Transfers......Page 398
12.2: Shift Registers......Page 402
12.3: Design of Binary Counters......Page 406
12.4: Counters for Other Sequences......Page 411
12.5: Counter Design Using S-R and J-K Flip-Flops......Page 417
12.6: Derivation of Flip-Flop Input Equations - Summary......Page 420
Problems......Page 424
Objectives......Page 434
Study Guide......Page 435
13.1: A Sequential Parity Checker......Page 441
13.2: Analysis by Signal Tracing and Timing Charts......Page 443
13.3: State Tables and Graphs......Page 447
13.4: General Models for Sequential Circuits......Page 454
Programmed Exercise 13.1......Page 458
Problems......Page 463
Objectives......Page 475
Study Guide......Page 476
14.1: Design of a Sequence Detector......Page 479
14.2: More Complex Design Problems......Page 485
14.3: Guidelines for Construction of State Graphs......Page 489
14.4: Serial Data Code Conversion......Page 495
14.5: Alphanumeric State Graph Notation......Page 498
14.6: Incompletely Specified State Tables......Page 500
Programmed Exercise 14.1......Page 502
Programmed Exercise 14.2......Page 504
Programmed Exercise 14.3......Page 506
Problems......Page 508
Objectives......Page 519
Study Guide......Page 520
15.1: Elimination of Redundant States......Page 527
15.2: Equivalent States......Page 529
15.3: Determination of State Equivalence Using an Implication Table......Page 531
15.4: Equivalent Sequential Circuits......Page 534
15.5: Reducing Incompletely Specified State Tables......Page 536
15.6: Derivation of Flip-Flop Input Equations......Page 539
15.7: Equivalent State Assignments......Page 541
15.8: Guidelines for State Assignment......Page 545
15.9: Using a One-Hot State Assignment......Page 550
Problems......Page 553
Objectives......Page 567
Study Guide......Page 568
16.1: Summary of Design Procedure for Sequential Circuits......Page 570
16.2: Design Example - Code Converter......Page 571
16.3: Design of Iterative Circuits......Page 575
16.4: Design of Sequential Circuits Using ROMs and PLAs......Page 578
16.5: Sequential Circuit Design Using CPLDs......Page 581
16.6: Sequential Circuit Design Using FPGAs......Page 585
16.7: Simulation and Testing of Sequential Circuits......Page 587
16.8: Overview of Computer-Aided Design......Page 592
Design Problems......Page 594
Additional Problems......Page 600
Objectives......Page 607
Study Guide......Page 608
17.1: Modeling Flip-Flops Using VHDL Processes......Page 612
17.2: Modeling Registers and Counters Using VHDL Processes......Page 616
17.3: Modeling Combinational Logic Using VHDL Processes......Page 621
17.4: Modeling a Sequential Machine......Page 623
17.5: Synthesis of VHDL Code......Page 630
17.6: More about Processes and Sequential Statements......Page 633
Problems......Page 635
Simulation Problems......Page 646
Objectives......Page 648
Study Guide......Page 649
18.1: Serial Adder with Accumulator......Page 651
18.2: Design of a Binary Multiplier......Page 655
18.3: Design of a Binary Divider......Page 659
Programmed Exercise 18.1......Page 666
Programmed Exercise 18.2......Page 668
Problems......Page 670
Objectives......Page 682
Study Guide......Page 683
19.1: State Machine Charts......Page 684
19.2: Derivation of SM Charts......Page 689
19.3: Realization of SM Charts......Page 694
Problems......Page 699
Objectives......Page 706
Study Guide......Page 707
20.1: VHDL Code for a Serial Adder......Page 710
20.2: VHDL Code for a Binary Multiplier......Page 712
20.3: VHDL Code for a Binary Divider......Page 722
20.4: VHDL Code for a Dice Game Simulator......Page 724
20.5: Concluding Remarks......Page 727
Problems......Page 728
Lab Design Problems......Page 731
Appendix A: MOS and CMOS Logic......Page 735
Appendix B: VHDL Language Summary......Page 741
Appendix C: Tips for Writing Synthesizable VHDL Code......Page 746
Appendix D: Proofs of Theorems......Page 749
Appendix E: Answers to Selected Study Guide Questions and Problems......Page 751
References......Page 807
Index......Page 808
