Functionality-Enhanced Devices: An alternative to Moore's Law

Cover
Contents
1 Introduction to functionality-enhanced devices
1.1 General background
1.1.1 Advanced transistor scaling
1.1.2 Emerging devices
1.1.2.1 Unconventional channel materials
1.1.2.2 Sub-60 mV/decade swing FETs
1.1.2.3 Functionality-enhanced devices
1.1.3 Toward nanosystems
1.2 Book organization
Acknowledgments
References
Part I Materials and device research related to functionality-enhanced devices
2 Germanium-based polarity-controllable transistors
2.1 Introduction
2.2 Theory and device simulations
2.3 Fabrication of polarity-controllable germanium nanowire transistors
2.4 Electrical characteristics of polarity-controllable germanium nanowire transistors
2.5 Benchmark and perspectives
2.6 Conclusions
Acknowledgments
References
3 Two-dimensional materials for functionality-enhanced devices
3.1 2D materials for functionality-enhanced devices
3.1.1 Introduction
3.1.2 Non-carbon 2D materials with bandgaps
3.1.2.1 Hexagonal boron nitride
3.1.2.2 Phosphorene
3.1.2.3 Transition metal dichalcogenides
3.2 Large area growth of 2D materials
3.2.1 Introduction
3.2.1.1 Chemical vapor deposition
3.2.1.2 Metal–organic chemical vapor deposition
3.2.1.3 Molecular beam epitaxy
3.3 Metal–semiconductor contacts and 2D heterostructures
3.4 2D materials for steep slope devices
3.4.1 Band to band carrier tunneling (BTBT) in 2D systems
3.4.2 Tunnel field effect transistors
3.4.3 Resonant tunneling devices/diodes
3.5 Circuit and system applications
3.5.1 RF applications
3.6 List of abbreviations
References
4 WSe2 polarity-controllable devices
4.1 Two-dimensional transition metal dichalcogenides
4.1.1 Synthesis of two-dimensional materials
4.1.2 Value of ambipolarity
4.2 Polarity-controllable devices on WSe2
4.3 Quantum transport simulations
4.4 Summary
References
5 Carrier type control of MX2 type 2D materials for functionality-enhanced transistors
5.1 MX2 materials
5.1.1 2D materials for FEDs
5.1.2 Crystalline structure and electric characteristics of TMDCs
5.2 MX2 materials in transistors
5.2.1 Need for 2D materials channel in advanced FETs
5.2.2 Carrier doping
5.2.3 Carrier injection via Schottky junctions
5.2.4 Fermi level pinning
5.3 Polarity controllable transistors on MoTe2
5.3.1 Ambipolar channels for polarity controllable transistors
5.3.2 MoTe2 channel
5.3.3 Single top gate device on MoTe2
5.3.4 Dual top-gate device on MoTe2
5.3.5 Issues in top-gate dielectrics
5.4 Enhanced ambipolarity by Schottky junction engineering in MoTe2
5.4.1 Schottky junctions in MoTe2
5.4.2 Barrier heights of MoTe2 Schottky junctions
5.4.3 Enhanced ambipolarity in MoTe2
5.5 Conclusions
References
6 Three-independent gate FET's super steep subthreshold slope
6.1 Introduction
6.2 Subthreshold slope
6.3 TIGFET background
6.4 TIGFET working principle
6.5 Structure and fabrication of TIGFETs
6.5.1 Device structure and fabrication
6.6 SS dependency in TIGFETs
6.6.1 Experimental dependency on voltage
6.6.2 Origin of voltage dependency
6.6.2.1 Body effect
6.6.2.2 Activation energy
6.6.3 Experimental dependency on temperature
6.6.4 Origin of temperature dependency
6.7 SS behavior from device simulations
6.7.1 TCAD Sentaurus design
6.7.2 SS dependency on long-channel devices
6.7.3 SS dependency on voltage
6.7.4 SS dependency on TIGFET's short-channel effects
6.8 Conclusion
Acknowledgment
References
7 Super sensitive terahertz detectors
7.1 Principles of THz detection in FETs
7.1.1 Dyakonov–Shur model
7.1.2 Theoretical formalism and modes of operation
7.1.3 Nonresonant detection: principles and advantages of subthreshold biasing
7.2 Overview of THz detectors and state of the art
7.2.1 Recent progress on nanowire-based THz detectors
7.2.2 Recent progress on graphene-based THz detectors
7.3 Emerging FET devices for THz detection applications: dual independent gate FinFET with super-steep subthreshold slope
7.3.1 A continuous compact DC model
7.3.2 Noise-equivalent power predictions
7.4 Conclusions
References
Part II Applications and design techniques of functionality-enhanced devices
8 CNT and SiNW modeling for dual-gate ambipolar logic circuit design
8.1 Desired model characteristics
8.1.1 Connection to underlying physics
8.1.2 Experimental matching
8.1.3 SPICE compatibility
8.1.4 PG modulation
8.1.5 Dynamic polarity switching (interchangeability)
8.2 Single-gate physically derived models
8.2.1 Unipolar SPICE model for ballistic CNTFETs
8.2.2 Unipolar Verilog-A model for doped CNTFETs
8.2.3 Ambipolar VHDL-AMS model for CNTFETs
8.2.4 Experimental matching
8.2.5 Connection to underlying physics
8.2.6 SPICE compatibility
8.2.7 PG modulation
8.2.8 Dynamic polarity switching (interchangeability)
8.3 Behavioral ambipolar models
8.3.1 Ambipolar model for double-independent-gate FinFETs
8.3.2 Ambipolar Verilog-A model for CNTFETs
8.3.3 Connection to underlying physics
8.3.4 Experimental matching
8.3.5 SPICE compatibility
8.3.6 PG modulation
8.3.7 Dynamic polarity switching (interchangeability)
8.4 Comprehensive semiconductor compensation simulation
8.4.1 Ambipolar TCAD simulation for WSe2FETs
8.4.2 Ambipolar TCAD simulation for SiNWFETs
8.4.3 Connection to underlying physics
8.4.4 Experimental matching
8.4.5 SPICE compatibility
8.4.6 PG modulation
8.4.7 Dynamic polarity switching (interchangeability)
8.5 Physical ambipolar models
8.5.1 MATLAB model for multiple-independent-gate FETs
8.5.2 Ambipolar VHDL-AMS model with binary PG for CNTFETs
8.5.3 Ambipolar Verilog-A model for CNTFETs
8.5.4 Ambipolar model for SiNWFETs
8.5.5 Connection to underlying physics
8.5.6 Experimental matching
8.5.7 SPICE compatibility
8.5.8 PG modulation
8.5.9 Dynamic polarity switching (interchangeability)
8.6 Ambipolar models with dynamic polarity
8.6.1 Dynamic Verilog-A model with fixed source and drain for CNTFETs
8.6.2 Dynamic Verilog-A model with source–drain interchangeability for CNTFETs
8.6.3 Connection to underlying physics
8.6.4 Experimental matching
8.6.5 SPICE compatibility
8.6.6 PG modulation
8.6.7 Dynamic polarity switching (interchangeability)
8.7 Summary
References
9 Physical design of polarity controllable transistors
9.1 Introduction
9.1.1 IC design and FPGA–ASIC gap
9.1.2 Ambipolar devices for Moore's law extension
9.1.3 Physical design objectives
9.2 Background
9.2.1 Structured ASICs
9.2.1.1 General concept
9.2.1.2 Tile granularity
9.2.2 SiNWFET physical design concepts
9.2.2.1 Sea-of-tiles with SiNWFETs
9.2.2.2 Satisfiable SoT (SATSoT)
9.2.2.3 Power routing of ambipolar designs
9.3 SiNWFET tile layout and placement and routing
9.3.1 Tile configuration for FinFETs
9.3.2 Tile configuration for SiNWFETs
9.3.3 Pin and layout generation
9.3.3.1 Intra-tile connection generation
9.3.3.2 Inter-tile connection generation
9.4 SOCE configuration
9.4.1 Placement schemes
9.4.1.1 Standard cell approach
9.4.1.2 Tile cell approach
9.4.2 Power routing schemes
9.4.2.1 Standard cell power routing scheme
9.4.2.2 Tile cell power routing scheme
9.5 Results and comparisons
9.5.1 Benchmarking methodology
9.5.1.1 Benchmark categories
9.5.1.2 Benchmark summary
9.5.1.3 Performance metrics
9.5.2 Benchmark results
9.5.2.1 Results for control and sequential designs
9.5.2.2 Results for arithmetic combinational designs
9.5.3 Comparisons and conclusions
9.5.3.1 Area increase analysis
9.5.3.2 Speed-up analysis
9.5.3.3 Design interconnection analysis
9.5.3.4 Metal distribution analysis
9.5.3.5 Result summary
9.6 Conclusions
References
10 BCB benchmarking for three-independent-gate field effect transistors
10.1 Introduction
10.2 TIGFET principles
10.2.1 Generalities
10.2.2 Fabrication techniques
10.2.3 Working principle
10.2.4 Logic behavior
10.3 Device-level considerations
10.3.1 Electrical properties
10.3.2 Capacitance consideration
10.3.3 Layout considerations
10.4 Circuit-level opportunities
10.5 Performance evaluation
10.5.1 Area estimation
10.5.1.1 Area summary
10.5.2 Delay estimation
10.5.3 Energy estimation
10.5.4 Standby power estimation
10.6 Comparison of technologies
10.6.1 Device-level performance
10.6.2 Circuit-level performance
10.6.3 Origin of EDP results
10.7 Conclusion
Acknowledgment
References
11 Exploratory logic synthesis for multiple independent gate FETs
11.1 Introduction
11.2 Survey on emerging MIGFETs
11.2.1 Double-gate silicon nanowire field effect transistor
11.2.2 Independent-gate-FinFET-LVth
11.2.3 Independent-gate-FinFET-HVth
11.2.4 Triple-gate-floating-gate metal-oxide-semiconductor (MOS)
11.2.5 Triple-gate-silicon nanowire field effect transistor
11.2.6 Logic abstraction and discussion
11.3 Logic synthesis for MIGFETs
11.3.1 Brief overview on logic synthesis
11.3.2 Circuit design considerations
11.3.3 Synthesis methodology
11.4 Experimental results
11.4.1 Methodology
11.4.1.1 Benchmarks MIGFETs
11.4.1.2 Estimation models
11.4.1.3 Synthesis tool
11.4.2 Results
11.4.3 Discussion
11.5 Custom exploration of special MIGFET classes
11.5.1 Potential of XOR MIGFETs
11.5.2 Potential of MAJ MIGFETs
11.5.3 Summary
11.6 Conclusions
References
12 Ultrafine grain FPGAs with polarity controllable transistors
Abstract
12.1 Background
12.1.1 FPGA architecture
12.1.2 Transistors with controllable polarity
12.1.3 Ultrafine grain reconfigurable logic gates
12.2 Leveraging the ultrafine granularity at the architecture level
12.2.1 Multilayer organization
12.2.2 Intramatrix interconnecting
12.2.3 Integration into FPGA architecture
12.3 MCluster CAD flow
12.3.1 General overview of the flow
12.3.2 MPack: the matrix packer
12.3.3 Matrix mapping algorithm
12.3.3.1 Architectural optimization
12.3.3.2 Mapping algorithm
12.3.4 Clustering algorithm
12.4 Experimental results
12.4.1 Methodology
12.4.2 Impact of the granularity
12.4.3 Performance comparison with CMOS
12.5 Conclusion
References
13 Tunnel FET-based security primitive design
13.1 Introduction
13.2 Background
13.2.1 Light-weight cipher
13.2.2 Current mode logic
13.3 Tunnel FET
13.3.1 Device description
13.3.2 Device modeling
13.4 Tunnel FET in hardware security
13.4.1 TFET-based current mode logic
13.4.2 TFET-based CML standard cells
13.4.3 CML implementation on KATAN
13.4.4 Correlation power analysis on KATAN32
13.5 Discussion
13.6 Conclusion
Acknowledgment
References
Index
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