This book provides a step-by-step methodology and system design that can be used to design a fully integrated PMU using SC DC-DC converters, for any CMOS technology. The authors discuss trade-offs between power density and efficiency of the methodology for the 130 nm CMOS technology, and how to implement it on other CMOS technologies. The book describes the state-of-the-art of fully or near-fully integrated SC DC-DC converters with multiple conversion ratios and the techniques used to enhance the overall performance of these converters. Coverage includes the trade-off between the number of conversion ratios and overall extracted efficiency from a supercapacitor, as well as the sizing of the converter cells according to the desired output power and maximum clock frequency. The authors also describe in detail the design of the fundamental blocks for the converter operation, which includes a secondary control loop using capacitance modulation by sensing the clock frequency.
Author(s): Ricardo Madeira, João Pedro Oliveira, Nuno Paulino
Series: Synthesis Lectures on Engineering, Science, and Technology
Publisher: Springer
Year: 2022
Language: English
Pages: 173
City: Cham
Preface
Acknowledgements
Contents
Acronyms
1 Introduction
1.1 Motivation
1.2 Outline
2 Switched-Capacitor DC-DC Fundamentals
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2.1 Capacitor Implementation in CMOS
2.1.1 Metal-Oxide-Semiconductor Capacitors
2.1.2 Metal-Insulator-Metal Capacitors
2.1.3 Metal-Oxide-Metal Capacitors
2.1.4 Exotic Capacitors
2.2 Switch Implementation
2.3 Theoretical SC DC-DC Analysis
2.4 Basic Voltage Regulation Technique
3 Fully Integrated Switched-Capacitor DC-DC State of the Art
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3.1 Topologies for Multi-ratio Fully Integrated SC DC-DC Converters
3.1.1 Series-Parallel Topology
3.1.2 Dickson Topology
3.1.3 Customized Topologies
3.1.4 Cascaded Topologies
3.2 Conclusions
4 Fully Integrated SC DC-DC Performance Enhancement Techniques State of the Art
4.1 Efficiency Enhancement Techniques
4.1.1 MOS Capacitor Parasitic Reduction Techniques
4.1.2 Charge Recycling
4.1.3 Stage Outphasing
4.1.4 Multiphase Soft-Charging
4.1.5 Full Soft-Charging Converter
4.1.6 Conclusions
4.2 Ripple Reduction Techniques
4.2.1 Conclusions
4.3 Dynamic Power Allocation Technique
4.3.1 Conclusions
4.4 Distributive Clock Generation
5 Design of a Fully Integrated Power Management Unit
5.1 Overview
5.2 Multi-ratio Multi-cell Fully Integrated SC DC-DC Converter Design
5.2.1 Topology and Conversion Ratio Selection
5.2.2 Switch Selection
5.2.3 Efficiency and Conversion Ratio Limits
5.2.4 Time Interleaved and Capacitance Modulation
5.3 Auxiliary Circuits Design
5.3.1 Phase Generator and Loop Regulation
5.3.2 Voltage Reference Generator
5.3.3 Switches' Drivers
5.3.4 Conversion Ratio Controller
5.3.5 Cell Controller
5.3.6 Start-Up Circuit
6 Fully Integrated Power Management Unit Layout, Simulation and Measurements Results
6.1 Overview
6.2 Power Management Unit Layout and Floorplan
6.2.1 Converter Cell Layout
6.2.2 Digital Blocks Layout
6.2.3 Analogue Blocks Layout
6.2.4 Simulation Results
6.2.5 Test Board and Measurements Setup
6.2.6 Prototype Measurements
7 Conclusions and Future Work
7.1 Conclusions
7.2 Future Work
A Appendix
A.1 PMU 16 mW Design
A.1.1 Design Equations of the 1/2 CR
A.1.2 Design Equations of the 2/3 CR
A.1.3 Design Equations of the 1/1 CR
A.1.4 PMU Switches' Resistance Sizing
