Frontiers of Quality Electronic Design (QED): AI, IoT and Hardware Security

Preface
Acknowledgements
Contents
About the Authors
NAND Flash Memory Devices Security Enhancement Based on Physical Unclonable Functions
1 Multimode Physical Unclonable Function as an Entropy Source for Generating True Random Bits
1.1 Introduction
1.2 General Description of a Circuit
1.3 Operation of the Entropy Source
1.3.1 Initial Memory
1.3.2 Ring Oscillator
1.3.3 Metastability
1.3.4 Latch
1.4 Experimental Results
1.4.1 Initial Memory
1.4.2 Ring Oscillator
1.4.3 Metastability
1.4.4 Latch
1.5 Conclusion
2 Raw Read-Based Physical Unclonable Function for TLC NAND Flash
2.1 Introduction
2.2 Control of the Entropy Source
2.2.1 Enrollment
2.2.2 Generation
2.3 Experimental Results
2.3.1 Enrollment
2.3.2 Generation
2.4 Conclusion
3 Flash Memory Device Identification Based on Physical Unclonable Functions
3.1 Introduction
3.2 ID Generation Algorithm
3.3 Example of ID Generation
3.4 Experimental Results
3.4.1 Reliability
3.4.2 Uniqueness
3.5 Conclusion
4 Design of Data Scrambler with Enhanced Physical Security
4.1 Introduction
4.2 Proposed Scrambler Circuit Operation
4.3 Experimental Results
4.3.1 Option 1
4.3.2 Option 2
4.4 Conclusion
5 Physical Unclonable Function-Based Error Detection Algorithm for Data Integrity
5.1 Introduction
5.2 Proposed Data Path Design
5.3 Example of Usage in Mobile NAND Flash Devices
5.4 Conclusion
6 Conclusion
Appendix
References
ReRAM-Based Neuromorphic Computing
1 Introduction
2 The Memristor
3 ReRAM: Implementation of the Memristor
4 Comparison of ReRAMs with Other Memory Technologies
5 Use of ReRAMs as Synapses
6 Use of ReRAMs as Neurons
7 ReRAMs in Neuromorphic Computing
8 ReRAM Crossbars
9 ReRAM-Based Spiking Neural Network
10 Spike Time-Dependent Plasticity
11 STDP Functionality in ReRAMs
12 ReRAM-Based SNN Architectures
13 Other ReRAM-Based Neural Networks
14 Conclusion
References
Flash: A ``Forgotten'' Technology in VLSI Design
1 Chapter Summary
2 Technology Overview
2.1 Flash Transistors
2.2 Pseudo-Flash Transistor
3 ASIC Replacement
3.1 Digital Circuit Design Using Flash Transistors
3.1.1 Flash-Based Digital Circuit Implementation
3.1.2 Flash-Based Implementation Results
3.1.3 Tuning Delay, Power, and Energy
3.1.4 Flash-Based Design Conversion
3.1.5 Performance of Our Conversion Flow
3.1.6 Conclusion
3.2 Perceptron Hardware: Flash Threshold Logic Cells
3.2.1 Flash Threshold Logic (FTL) Cell Architecture
3.2.2 Related Work
3.2.3 Experimental Results
3.2.4 Summary
3.3 Input and Output Hybridization for Enhanced Security in ASIC Circuits
3.3.1 Security and Hybridization
3.3.2 Previous Work
3.3.3 SAT-Based Threshold Function Identification and Weight Generation
3.3.4 Results
3.4 Benefits of Flash-Based ASIC Design
4 Neural Network Accelerators
4.1 A Configurable BNN ASIC Using a Network of Programmable Threshold Logic Standard Cells
4.1.1 Binary Neural Network Using Binary Neurons
4.1.2 Hardware Architecture of TULIP-PE
4.1.3 Addition and Accumulation Operation
4.1.4 Comparison, Batch Normalization, Max Pooling, and RELU Operation
4.1.5 Top-Level View of the Architecture
4.1.6 Experimental Results
4.1.7 Conclusion
4.2 A Flash-Based Current-Mode IC to Realize Quantized Neural Networks
4.2.1 Fully Connected (FC) Node Design
4.2.2 Convolution (CONV) Node Design
4.2.3 MAXPOOL
4.2.4 Batch Normalization
4.2.5 Dataflow Architecture
4.2.6 Experiment and Results
4.2.7 Conclusion
5 CIDAN: Computing in DRAM with Artificial Neurons
5.1 Introduction
5.2 Threshold Logic Processing Element (TLPE)
5.3 Top-Level Architecture of CIDAN
5.4 System-Level Integration and the Controller Design
5.5 Experimental Results
5.6 Conclusion
6 Flash Devices in Analog Circuits
6.1 Flash-Based Digital to Analog Conversion
6.1.1 Design
6.1.2 Features
6.1.3 Performance Metrics
6.1.4 Summary
6.2 Pseudo-Flash-Based Digital Low-Dropout Regulator
6.2.1 Proposed Pseudo-Flash-Based Digital LDO
6.2.2 Coarse-Fine Controller
6.2.3 Simulation Results
6.3 Summary
7 Conclusions and Future Outlook
References
Nonvolatile Memory Technologies: Characteristics, Deployment, and Research Challenges
1 Introduction
2 Characteristics of NVM Devices
2.1 Flash Storage Devices
2.2 Phase Change Memory (PCM)
2.3 Resistive Random Access Memory (ReRAM/RRAM)
2.4 Ferro-Electric Random Access Memory (FeRAM)
2.5 Carbon Nanotube Random Access Memory (NRAM)
2.6 Spin-Transfer Torque RAM (STT-RAM)
3 Deployment of Nonvolatile Memories in Computing System
3.1 Deploying NVM Devices as Processor Cache
3.2 Integrating NVM as Main Memory
3.2.1 Replacing Conventional Memory Devices with NVM
3.2.2 Integrating NVM and DRAM as Hybrid Memories
3.3 Deploying NVM as Storage
4 Challenges in Adopting NVM Devices at Different Levels of Memory
4.1 Design Issues in Utilizing NVM as Cache
4.1.1 Management of Hybrid Caches
4.1.2 Challenges in Adopting Hybrid Caches
4.2 Challenges in Adapting NVM as a Candidate for Hybrid Memories
4.3 Challenges in Adopting NVM as Storage Media
4.3.1 Changes to the Operating System
4.3.2 Modifications in the File System
5 Current Research Challenges
5.1 Lifetime Improvement
5.1.1 Wear-Leveling Techniques
5.1.2 Write Reduction Techniques
5.1.3 Error Correction
5.2 Multilevel Cell
5.2.1 Multilevel Cell Property in PCM
5.2.2 Multilevel Cell Property in ReRAM
5.2.3 Multilevel Cell Property of STT-RAM
5.2.4 Multilevel Cell of FeRAM
5.3 Accelerators
5.4 Security
6 Application of NVM Devices in IoT and AI
7 Simulators
8 Conclusions and Future Scope
References
Data Analytics and Machine Learning for Coverage Closure
1 Introduction
2 Descriptive Coverage Analysis
2.1 Coverage Views
2.1.1 Selections
2.1.2 Projections
2.1.3 Groupings
2.2 Hole Analysis: Automatic Descriptive Coverage Analysis
2.2.1 Algorithm for Projected Holes
2.2.2 Algorithm for Aggregated Holes
2.3 Machine Learning-Based Discovery of Coverage Model Structure
2.3.1 Clustering Events into Cross-Products
2.3.2 Improving the Cross-Product Quality
2.3.3 Usage Results
3 Template Aware Coverage
3.1 TAC Use-Cases and Queries
3.1.1 Best Test-Templates to Hit an Event
3.1.2 Best Test-Templates to Hit a Coverage Model
3.1.3 Coverage of a Test-Template
3.1.4 Uniquely Hit Events
3.1.5 Aged-Out Events
3.2 Implementation
3.2.1 Data Structures
3.2.2 Sparse Matrix Operations
3.2.3 Performance
4 Automatic Coverage Closure
4.1 Coverage-Based Regression
4.1.1 Finding an Optimized Test Policy
4.1.2 Mapping Verification Goals to TAC-Optimized Test Policies
4.2 Coverage-Directed Generation
4.2.1 Problem Definition
4.2.2 Approximated Target Function
4.2.3 Random Sample
4.2.4 Optimization
4.2.5 Combining Random Sampling and Optimization
4.3 CDG for Large Sets of Events
4.3.1 Event After Event Implicit Filtering for Multiple Targets
4.3.2 Machine Learning Accelerated Implicit Filtering
4.3.3 Experimental Results
5 Conclusions
References
Cell-Aware Model Generation Using Machine Learning
1 Introduction
2 Background on Standard Cell Characterization
2.1 Standard Cell Characterization for Design Purpose
2.2 Cell Internal Defect Universe
2.3 Standard Cell Characterization for Test and Diagnosis Purpose
2.4 Cell-Aware Model Generation: A Machine-Learning Friendly Process
3 Learning-Based Cell-Aware Model Generation Flow
3.1 Generation of Training Data
3.2 Generation of New Data
4 Cell and Defect Representation in the Cell-Aware Matrix
4.1 Identification of Active, Passive, and Pulsing Transistors
4.2 Renaming of Transistors
4.2.1 Determination of Branch Equations
4.2.2 Sorting of Branch Equations
4.3 Identification of Parallel Transistors
4.4 Defect Representation in the Cell-Aware Matrix
5 Validation on Industrial Cell Libraries
5.1 Predicting Defect Behavior on the Same Technology
5.1.1 Combinational Standard Cells
5.1.2 Sequential Standard Cells
5.2 Predicting Defect Behavior on Another Technology
5.2.1 Combinational Standard Cells
5.2.2 Analysis and Discussion
5.2.3 Sequential Standard Cells
5.2.4 Controlled Experiments
6 Hybrid Flow for CA Model Generation
6.1 Runtime Saving for Combinational Cells
6.2 Runtime Saving for Sequential Cells
7 Discussion and Conclusion
References
Neuromorphic Computing: A Path to Artificial Intelligence Through Emulating Human Brains
1 Introduction
2 Biological Neural System
2.1 Neurons and Synapses
2.2 Associative Memory Learning
3 Modeling Neural System
3.1 Leaky Integrate and Fire Neuron Model
3.2 Hodgkin-Huxley Neuron Model
3.3 Izhikevich Neuron Model
3.4 McCulloch-Pitts Neuron Model
3.5 Neural Coding
4 Silicon Brain
4.1 Electronic Neurons
4.2 Memristive Synapses
5 Neuromorphic Chips
5.1 Loihi Chips
5.2 Dynamic Neuromorphic Asynchronous Processors
5.3 TrueNorth Chips
5.4 Neurogrid Chips
5.5 BrainScaleS Project
5.6 Human Brain Project
6 Challenges and Opportunities
References
AI for Cybersecurity in Distributed Automotive IoT Systems
1 Introduction
2 Related Work
3 Background on Sequence Learning
3.1 Sequence Models
3.1.1 Recurrent Neural Network (RNN)
3.1.2 Long Short-Term Memory (LSTM) Networks
3.1.3 Gated Recurrent Unit (GRU)
3.2 Autoencoders
4 Definitions and Problem Formulation
4.1 System Model
4.2 Communication Model
4.3 Attack Model
5 INDRA Framework Overview
5.1 Recurrent Autoencoder
5.1.1 Model Architecture
5.1.2 Training Procedure
5.2 Inference and Detection
6 Experiments
6.1 Experimental Setup
6.2 Intrusion Threshold Selection
6.3 Comparison of INDRA Variants
6.4 Comparison with Prior Works
6.5 IDS Overhead Analysis
6.6 Scalability Results
7 Conclusion
References
Ultralow-Power Implementation of Neural Networks Using Inverter-Based Memristive Crossbars
1 Introduction
2 Literature Review
2.1 Memristor
2.2 Memristive Neuron Circuit
2.3 Memristor Non-idealities
3 Mathematical Analysis
3.1 Circuit Model of an IM Neuron
3.2 Effects of Non-idealities on the Outputs of IM Neurons
3.2.1 Variations of the Activation Functions Coefficients
3.2.2 IM Neuron Output Sensitivity to the Conductance Variation of Memristors
3.2.3 IM-NN Primary Output Sensitivity to Characteristic Variations of Circuit Elements
3.3 Inductions Drawn from the Above Analysis
4 Input/Output Interfaces
4.1 Memristive DAC
4.2 Memristive ADC
5 Training of IM-NNs
5.1 PHAX
5.2 RIM
5.3 LATIM
5.4 ERIM
5.4.1 Implementation of Adjustable-Size Inverters
5.5 OCTAN
6 Variation Mitigation Methods
6.1 Variation-Aware Training (VAT)
6.2 INTERSTICE
7 Comparison of Different Training Methods
7.1 Training Methods
7.2 IM-NN Accuracy in the Presence of Variations
7.3 Comparing Different Training Methods
7.4 Opportunities for Future Research
References
AI-Based Hardware Security Methods for Internet-of-Things Applications
1 Introduction
2 Hardware Attacks
2.1 IP Piracy
2.2 Reverse Engineering
2.3 Counterfeiting
2.4 Hardware Trojans
2.5 Side-Channel Attacks
3 Countermeasures Against Side-Channel Attacks and Hardware Trojans Insertion
3.1 Generic Countermeasures for SCA
3.2 Generic Countermeasures Against Hardware Trojan Insertions
3.3 Countermeasures Against Physical Attacks in IoT
3.4 Countermeasures Against Hardware Trojans in IoT
4 Unified Countermeasures for IoT
5 3D ICs and Machine Learning
6 Securing IoT Infrastructure Using Artificial Intelligence (AI) and Machine Learning (ML)
6.1 Hardware Trojan Detection Using AI and ML
6.2 Hardware Trojan Detection in IoT Systems Using AI and ML
7 Leveraging 3D Integration for Hardware Security in IoT Devices
8 Discussion
References
Enabling Edge Computing Using Emerging Memory Technologies: From Device to Architecture
1 Introduction and Motivations
1.1 Von-Neumann vs. Non-Von-Neumann Architectures
1.2 Normally Off Computing Systems
2 Emerging Magnetic RAM (MRAM) Technology
2.1 STT-MRAM
2.2 SOT-MRAM
3 Enabling Data-Intensive Computing Paradigm
3.1 General Processing-in-Memory Structure
3.2 Circuit-Level Exploration: Evolution of the MRAM-Based PIM Platforms
3.2.1 Basic PIM Supporting (N)AND, (N)OR
3.2.2 Reconfigurable Complete PIM Supporting X(N)OR
3.2.3 Reconfigurable PIM Supporting Two-Cycle In-Memory Addition
3.2.4 Reconfigurable PIM Supporting One-Cycle In-Memory Addition
3.3 Convolutional Neural Networks (CNN) Acceleration: Analog or Digital PIM Approach?
3.3.1 CNN Terminology
3.3.2 Evaluation Framework
3.3.3 Performance Analysis
4 Enabling Reliable and Resilient Computing Paradigm
4.1 MG-Based Synthesis and Optimization Research Tool
4.1.1 Technology-Dependent Optimization
4.1.2 Power and Delay Optimization
4.1.3 Area Optimization
4.2 Power Failure Resilient: NV-Clustering Design Methodology
4.2.1 Logic-Embedded FF (LE-FF) Design
4.2.2 NV-Clustering Methodology
4.2.3 Simulation Results
4.3 Power Analysis Resilient: PARC Design Methodology
4.3.1 PARC Design Methodology
5 Conclusion
References
IoT Commercial and Industrial Applications and AI-Powered IoT
1 Introduction
2 IoT Commercial Applications
2.1 Healthcare
2.1.1 Clinical Sensors
2.1.2 Nonclinical Sensors
2.2 Tourism and Hospitality
2.3 Retail Industry
2.4 Digital Marketing
3 IoT Commercial Applications
3.1 Agriculture
3.1.1 Field Sensors
3.1.2 Climate Sensors
3.2 Oil and Gas Mining
3.2.1 Smart Pipelines
3.2.2 Lone Worker Monitoring
3.2.3 Safety and Security
3.3 Wearables
3.3.1 Fitness Trackers
3.3.2 Smartwatches
3.3.3 Accelerometers
3.4 Smart Cities
3.4.1 Environmental Monitoring
3.5 Smart Buildings
3.6 Maintenance Management
3.7 Water Supply
3.8 Manufacturing
3.9 Transportation
3.10 Warehouses
4 IoT Security and Privacy Issues
4.1 IoT Malware
4.2 Encrypted Threats
4.3 Perception Layer
4.3.1 Node Capture
4.3.2 Replay Attack
4.3.3 Malicious Node
4.4 Network Layer
4.4.1 DDoS (Distributed Denial-of-Service) Attack
4.4.2 Man-in-the-Middle Attack
4.4.3 Spoofing Attack
4.4.4 Wormhole Attack
4.4.5 Black Hole Attack or Drop Attack
4.4.6 Sybil Attack
4.4.7 Sinkhole Attack
4.4.8 Malicious Code Injection
4.5 Application Layer
4.5.1 Cross-Site Scripting
4.5.2 Privacy and Confidentiality
5 IoT Data Analytics
6 AI-Powered IoT
6.1 Benefits of AI-Powered IoT
6.1.1 Boosting Operational Efficiency
6.1.2 Better Risk Management
6.1.3 Triggering New and Enhanced Products and Services
6.1.4 Increase IoT Scalability
6.1.5 Eliminates Costly Unplanned Downtime
6.1.6 Smart Thermostat
7 Conclusion
References
Hardware and System Security: Attacks and Countermeasures Against Hardware Trojans
1 Introduction
2 IC Supply Chain
3 HT Structure
4 HT Models
5 HT Attacks
6 HT Taxonomy
7 Challenges Against HTs
8 Structure and Purpose of the Chapter
9 An Overview of Artificial Intelligence
9.1 Artificial Intelligence Term
9.2 Machine Learning Term
9.3 Deep Learning Term
10 Tasks of Learning
10.1 Supervised Learning
10.2 Unsupervised Learning
10.3 Semi-supervised Learning
11 Learning Models
11.1 Artificial Neural Network Models
11.2 Bayesian Models
11.3 Clustering Models
11.4 Computer Vision Models
11.5 Decision Tree Models
11.6 Deep Learning Models
11.7 Dimensionality Reduction Models
11.8 Ensemble Learning Models
11.9 Generative Learning Models
11.10 Instance-Based Models
11.11 Natural Language Processing Models
11.12 Regression Models
11.13 Regularization Models
11.14 Speech Recognition Models
12 AI History Timeline
13 Countermeasures Against HTs
14 Historical Throwback
15 Studies Trend
16 Side-Channel Analysis-Based Approaches
16.1 SCA Power Analysis-Based Approaches
16.2 SCA Time Analysis-Based Approaches
17 ML and Simulation-Based Approaches
17.1 Logic Testing Simulation Approaches
17.2 ML-Based Approaches
18 Auxiliary Approaches
18.1 Runtime Monitoring Approaches
18.2 Prevention and Facilitation Approaches
19 Build Your Model Against HTs
19.1 Dataset
19.2 Training of Our ML- and DL-Based Models
19.2.1 Gradient-Boosting Algorithm
19.2.2 K-Nearest Neighbor Algorithm
19.2.3 Multilayer Perceptron Algorithm
19.2.4 Random Forest Algorithm
19.2.5 Support Vector Machine Algorithm
19.2.6 GAN Algorithm
19.2.7 CGAN Algorithm
19.2.8 WGAN Algorithm
19.3 Evaluation
19.3.1 Metrics for Classification ML-Based Algorithms
19.3.2 Metrics for the Evaluation of GL-Based Algorithms
19.4 Hyperparameter Tuning
20 Languages, Frameworks, and Tools
21 Conclusions
References
FPGA Security: Security Threats from Untrusted FPGA CADToolchain
1 Introduction
2 Commercial and Open-Source FPGA CAD Tools
3 Security Threats from FPGA CAD Tools
3.1 Security Threats in Commercial FPGA CAD Tool
3.1.1 Attacks on Xilinx ISE
3.1.2 Attacks on Altera Quartus
3.1.3 Attack Surfaces Induced by Integrating Countermeasures to Commercial CAD Tools
3.2 Security Threats in Open-Source FPGA CAD Tool
3.2.1 Potential Attacks on VTR
3.2.2 Potential Attacks on Symbiflow
3.2.3 Practical Attacks Using Open-Source FPGA CAD Tools
3.2.4 Generalized Attack Flow in Open-Source FPGA CAD Tools
4 New Security Threat Landscape
4.1 New FPGA Utilization Model
4.2 New FPGA Security Challenges
4.3 Comprehensive Summary of Attack Surfaces
5 Conclusion and Future Research Directions
References
DoS Attack Models and Mitigation Frameworks for NoC-Based SoCs
1 Introduction
2 Threat Model
2.1 Wired NoC Threat Model
2.2 Wireless NoC Threat Model
3 DoS Attack Detection and Localization in wired NoC-Based SoCs
3.1 Attack Detection Framework
3.1.1 First-Level Sanity Check
3.1.2 Machine Learning for Attack Detection
3.1.3 Results and Analysis
3.2 Attack Localization Framework
3.2.1 Machine Learning for Localization
3.2.2 Algorithm for MIP Localization
3.2.3 Walk-Through Example
3.3 Results and Analysis
4 DoS Attack Detection and Localization in WNoC-Based SoCs
4.1 Possible Threat Model
4.1.1 Attacks on WNoC CAM
4.1.2 Trojan Attack Activation
4.2 Security Countermeasures
4.2.1 Ranking Based CAM
4.2.2 Attack Detection and Correction
4.3 Experimental Setup and Results
5 Conclusion and Future Work
References
Defense against Security Threats with Regard to SoC Life Cycle
1 Motivation
2 Security Threats with Regard to SoC Life Cycle and Supply Chain
3 Sources of Attacks in SoCs
3.1 Design Stage
3.2 Synthesis RTL to Layout
3.3 Fabrication and Manufacturing
3.4 In-Field Attacks
4 Threat Model
4.1 Hardware Trojan Attacks
4.2 Side-Channel Attacks
4.3 Fault Injection Attacks
4.4 Test-Infrastructure-Based Attacks
4.4.1 Differential Scan Attack (DSA)
4.4.2 Test-Mode-Only (TMO) Attack
5 Defense Against the Security Threats
5.1 State-of-the-Art Techniques for Hardware Trojan Detection
5.2 Countermeasures Against Side-Channel Attacks (SCA)
5.3 Countermeasures Against Fault Injection Attacks
5.4 Countermeasures Against Test-Infrastructure-Based Attacks
5.4.1 Countermeasures Against DSA Only
5.4.2 Countermeasures Against Test-Mode-Only Attack
5.4.3 Unified Countermeasures
6 Summary
References
Defect Diagnosis Techniques for Silicon Customer Returns
1 Introduction
2 Background on Test and Fault Diagnosis
2.1 From Defects to Failures
2.2 Testing
2.3 Fault Diagnosis
2.3.1 System-Level Fault Diagnosis
2.3.2 Digital Block-Level Fault Diagnosis
2.3.3 Cell-Aware Fault Diagnosis
3 Test of Customer Returns for Diagnosis Purpose
3.1 Typical Test Scenario
3.2 Limitation of Manufacturing Test for Customer Returns
3.3 Best Practices for Customer Return Test Pattern Generation
4 Defect Diagnosis Techniques for Customer Returns
4.1 Conventional Approaches
4.1.1 Diagnosis Using Fault Simulation
4.1.2 Diagnosis Using Critical Path Tracing
4.2 Advanced Methods Based on Machine Learning
4.2.1 Preliminaries
4.2.2 Learning-Based Cell-Aware Diagnosis Flow
5 Industrial Case Studies
5.1 Simulated Test Case Studies
5.2 Silicon Test Case Study
6 Discussion and Conclusion
References
Index