This book constitutes the refereed proceedings of the 5th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2004, held in Austin, Texas, USA in November 2004.
The 29 revised full papers presented together with the abstract of an invited talk were carefully reviewed and selected from 69 submissions. The papers address all current issues on tools, methods, algorithms, and foundational theory for the application of formalized reasoning to all aspects of computer-aided systems design, including specification, verification, synthesis, and testing.
Author(s): Wayne Wolf (auth.), Alan J. Hu, Andrew K. Martin (eds.)
Series: Lecture Notes in Computer Science 3312
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2004
Language: English
Pages: 448
Tags: Computer Hardware; Software Engineering; Logics and Meanings of Programs; Mathematical Logic and Formal Languages; Artificial Intelligence (incl. Robotics); Computer-Aided Engineering (CAD, CAE) and Design
Front Matter....Pages -
Challenges in System-Level Design....Pages 1-5
Generating Fast Multipliers Using Clever Circuits....Pages 6-20
Verification of Analog and Mixed-Signal Circuits Using Hybrid System Techniques....Pages 21-36
A Methodology for the Formal Verification of FFT Algorithms in HOL....Pages 37-51
A Functional Approach to the Formal Specification of Networks on Chip....Pages 52-66
Proof Styles in Operational Semantics....Pages 67-81
Integrating Reasoning About Ordinal Arithmetic into ACL2....Pages 82-97
Combining Equivalence Verification and Completion Functions....Pages 98-112
Synchronization-at-Retirement for Pipeline Verification....Pages 113-127
Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs....Pages 128-143
Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders....Pages 144-158
Scalable Automated Verification via Expert-System Guided Transformations....Pages 159-173
Simple Yet Efficient Improvements of SAT Based Bounded Model Checking....Pages 174-185
Simple Bounded LTL Model Checking....Pages 186-200
QuBE++ : An Efficient QBF Solver....Pages 201-213
Bounded Probabilistic Model Checking with the Mur φ Verifier....Pages 214-229
Increasing the Robustness of Bounded Model Checking by Computing Lower Bounds on the Reachable States....Pages 230-244
Bounded Verification of Past LTL....Pages 245-259
A Hybrid of Counterexample-Based and Proof-Based Abstraction....Pages 260-274
Memory Efficient All-Solutions SAT Solver and Its Application for Reachability Analysis....Pages 275-289
Approximate Symbolic Model Checking for Incomplete Designs....Pages 290-305
Extending Extended Vacuity....Pages 306-321
Parameterized Vacuity....Pages 322-336
An Operational Semantics for Weak PSL....Pages 337-351
Accepting Predecessors Are Better than Back Edges in Distributed LTL Model-Checking....Pages 352-366
Bloom Filters in Probabilistic Verification....Pages 367-381
A Simple Method for Parameterized Verification of Cache Coherence Protocols....Pages 382-398
A Partitioning Methodology for BDD-Based Verification....Pages 399-413
Invariant Checking Combining Forward and Backward Traversal....Pages 414-429
Variable Reuse for Efficient Image Computation....Pages 430-444
Back Matter....Pages -
