Flexible Electronics, Volume 2: Thin-film transistors

Preface
Acknowledgements
About the book
Author biography
Vinod Kumar Khanna
Abbreviations, acronyms, chemical symbols and formulae
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Mathematical symbols and general notation
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Chapter 1 Amorphous Si TFT
1.1 Thin-film transistor (TFT)
1.2 TFT configurations and structures
1.3 a-Si TFTs on polyimide foil substrates
1.3.1 TFTs on 51 μm and 25 μm thick polyimide foils
1.3.2 Significance of SiNx passivation layer
1.3.3 Optimization of deposition conditions of SiNx
1.3.4 TFT fabrication
1.3.5 TFT parameters
1.3.6 Effects of bending on TFTs
1.4 Effects of uniaxial and biaxial strain on TFTs
1.4.1 Effects of cylindrical deformation (uniaxial strain) on TFTs
1.4.2 Effects of spherical deformation of TFT islands (biaxial strain) on TFTs
1.5 TFTs on stainless steel foil substrates
1.5.1 Advantages of stainless steel substrates
1.5.2 TFTs on thin stainless steel substrates
1.5.3 TFTs on thin stainless steel substrates
1.6 TFTs on clear plastic (CP) foil substrates
1.6.1 Difficulties with common substrate materials
1.6.2 TFTs on clear plastic with temperature tolerance limit up to 180 °C
1.6.3 TFTs on clear plastic with temperature tolerance limit up to 250 °C–280 °C
1.6.4 TFTs on clear plastic by controlling mechanical stresses in substrate passivation and TFT structural layers
1.7 Minimizing the shift in threshold voltage of TFT for reliable AMOLED operation
1.7.1 Cruciality of high TFT processing temperature for AMOLED luminance stability
1.7.2 Conditions to achieve unwavering TFT characteristics
1.8 Discussion and conclusions
Review exercises
References
Chapter 2 PolySi TFT
2.1 Introduction
2.2 PolySi TFT on PET
2.2.1 Need for process re-optimization
2.2.2 Si crystallization by localized heating
2.2.3 TFT fabrication process
2.2.4 TFT parameters
2.3 PolySi TFT on PES
2.3.1 TFT fabrication
2.3.2 TFT performance
2.4 PolySi TFT on PES or PAR
2.4.1 TFT fabrication
2.4.2 TFT parameters
2.5 PolySi TFT on plastic film by laminating on glass carrier
2.5.1 TFT fabrication
2.5.2 TFT parameters
2.6 Low-temperature <425 °C polySi TFT by SUFTLA
2.6.1 TFT fabrication
2.6.2 SUFTLA process
2.7 TFTs on stainless steel foil
2.7.1 PolySi TFT on thin stainless steel foil
2.7.2 PolySi TFT on thick stainless steel foil
2.7.3 PolySi TFT circuit on stainless steel
2.8 Discussion and conclusions
Review exercises
References
Chapter 3 Single-crystal Si TFT
3.1 Introduction
3.2 Transferrable single-crystal silicon nanomembranes (NMs)
3.3 SOI wafer process for Si NMs production, doping and transfer
3.3.1 Basic questions
3.3.2 Formation of Si nanoribbons
3.3.3 Pre-release doping of nanomembranes
3.3.4 Transfer printing of nanomembranes
3.4 Microwave TFT fabrication using Si NMs
3.4.1 Process steps on SOI wafer
3.4.2 Process steps after transferring to PET substrate
3.4.3 TFT parameters
3.5 TFTs on strained Si/SiGe/Si NMs
3.5.1 Ion implantation, annealing and reduction of device layer thickness
3.5.2 Growth of SiGe alloy and Si films
3.5.3 Separation and release of the strips
3.5.4 Strain distribution in the trilayer after release of strips
3.5.5 Transfer of strips to PET substrate
3.5.6 TFT parameters
3.6 Discussion and conclusions
Review exercises
References
Chapter 4 Metal-oxide TFT
4.1 Introduction
4.2 IGZO TFT with ESL on PEN substrate
4.2.1 Coating the PEN substrate with a moisture barrier layer
4.2.2 Deposition of gate metal
4.2.3 Gate dielectric deposition
4.2.4 IGZO semiconductor deposition
4.2.5 Etch stop layer (ESL)
4.2.6 Making contact holes
4.2.7 Source/drain metallization and interconnections
4.2.8 Encapsulation with SU-8
4.2.9 Effect of bending on the device and circuit
4.3 IGZO TFT with cellulose fiber-based paper as substrate cum gate dielectric
4.3.1 IZO gate electrode deposition
4.3.2 IGZO semiconductor layer deposition
4.3.3 Source/drain contacts
4.3.4 TFT parameters on paper types A and B
4.4 IGZO TFT fabrication process by sol–gel route
4.4.1 Gate electrode
4.4.2 Gate dielectric
4.4.3 Preparation of IGZO precursor solution
4.4.4 Semiconductor channel layer
4.4.5 Via holes
4.4.6 Source/drain electrodes
4.4.7 Electrical characteristics of TFT
4.5 IGZO TFT with organic gate dielectric/moisture barrier layers
4.5.1 Attachment of PI film to rigid glass substrate
4.5.2 Organic barrier layer deposition
4.5.3 Organic gate electrode deposition
4.5.4 Organic gate dielectric deposition
4.5.5 IGZO active layer deposition
4.5.6 Source/drain electrode deposition
4.5.7 Detachment of TFT from the PDMS/glass substrate
4.5.8 Electrical and bending characteristics
4.6 Transparent Ni-doped ZnO TFT
4.6.1 Deposition of bottom ITO film as gate electrode
4.6.2 SiO2 gate insulator deposition
4.6.3 NZO channel layer deposition
4.6.4 ITO source/drain contact deposition
4.6.5 Optimized TFT characteristics
4.7 TFT with PEALD ZnO layer
4.7.1 Laminating the PI substrate on a glass carrier
4.7.2 Gate metal sputtering and patterning
4.7.3 Al2O3 and ZnO films by PEALD
4.7.4 Patterning ZnO and Al2O3 films
4.7.5 Patterning and sputtering of titanium source/drain electrodes
4.7.6 Passivation
4.7.7 Delamination of PI
4.7.8 Typical electrical characteristics
4.8 Discussion and conclusions
Review exercises
References
Chapter 5 Small organic molecule TFT
5.1 Introduction
5.2 Pentacene TFT on PEN substrate
5.2.1 Base film (substrate)
5.2.2 Gate dielectric
5.2.3 Semiconductor channel layer
5.2.4 Process
5.2.5 Measurements
5.3 Bending effects on pentacene TFT
5.3.1 TFT fabrication and characteristics
5.3.2 Bending experiments
5.4 Pentacene and F16CuPc TFTs on PEN substrate for organic complementary circuit
5.4.1 Substrate preshrinking
5.4.2 Definition of gate electrode and first interconnect level
5.4.3 Gate dielectric deposition
5.4.4 Creation of vias between first and second interconnect levels
5.4.5 Definition of source/drain contacts and second interconnect level
5.4.6 Deposition and patterning of pentacene film
5.4.7 Deposition of F16CuPc film
5.4.8 P-Channel and N-channel TFTs
5.4.9 Complementary circuit
5.5 N-type small-molecule perylene diimide TFT
5.5.1 Need of N-type TFTs
5.5.2 Fabrication of TFTs
5.5.3 Comparison of TIPS-pentacene TFT, PTAA TFT and perylene diimide TFT
5.6 DNTT TFTs and circuits
5.6.1 Proneness of organic semiconductor to oxidation
5.6.2 Synthesis of DNTT
5.6.3 The substrate
5.6.4 Gate electrodes
5.6.5 SAM/AlOx gate dielectric
5.6.6 DNTT film
5.6.7 Source/drain contacts
5.6.8 Vias between gate level and source/drain level
5.6.9 Stability of TFT parameters on exposure to air and light
5.6.10 DNTT TFT-based inverters and ring oscillators
5.7 DNTT TFT-based digital library
5.7.1 TFT fabrication
5.7.2 TFT parameters
5.8 Discussion and conclusions
Review exercises
References
Chapter 6 Polymer TFT
6.1 Introduction
6.2 P3HT TFT on polycarbonate substrate
6.2.1 Substrate
6.2.2 Gate dielectric
6.2.3 Semiconductor film
6.2.4 Process steps
6.2.5 TFT parameters
6.3 PTAA TFT on PET foil
6.3.1 Printing ink formulation
6.3.2 Formation of interdigitated source/drain structures by offset printing
6.3.3 PTAA semiconductor deposition
6.3.4 Semiconductor/insulator interface optimization
6.3.5 Deposition of BaTiO3 filled polymer as gate insulator
6.3.6 Deposition of carbon-filled polymer on gate and source/drain contact areas
6.3.7 TFT characteristics
6.4 PDQT TFT array on PET substrate
6.4.1 Substrate surface pretreatment and modification
6.4.2 Inkjet printing of PEDOT:PSS source/drain electrodes
6.4.3 Organic semiconductor PDQT film deposition
6.4.4 PMMA gate insulator layer deposition
6.4.5 Enhancement of wettability of PMMA surface
6.4.6 PEDOT:PSS gate printing
6.4.7 TFT characterization
6.5 Ultrathin, disintegrable PDPP–PD polymer TFT and logic circuits on cellulose substrate
6.5.1 Biodegradable substrate
6.5.2 Synthesis of decomposable PDPP–PD poly(diketopyrrolopyrrole–phenylenediamine) polymer
6.5.3 Fabrication of logic circuits
6.6 FBT–TH4(1, 4) TFT on PEN substrate
6.6.1 Substrate preparation
6.6.2 Gas and moisture barrier layer deposition
6.6.3 Al:Nd film deposition
6.6.4 Anodic oxidation of the Al:Nd film
6.6.5 SAM deposition
6.6.6 Organic semiconductor layer deposition
6.6.7 Source/drain electrodes
6.6.8 TFT characteristics and bending effects
6.7 Discussion and conclusions
Review exercises
References
Chapter 7 Organic single-crystal TFT
7.1 Introduction
7.2 Rubrene single-crystal TFT
7.2.1 Growth of rubrene single crystal
7.2.2 Source/drain/gate electrodes
7.2.3 Adhering the rubrene crystal to the electrode pattern
7.2.4 Electrical characteristics of the TFT
7.2.5 Tolerance to bending
7.3 BPEA single-crystal TFT
7.3.1 Formation of gate electrode
7.3.2 Formation of source/drain electrodes
7.3.3 Growth of BPEA single-crystal ribbon
7.3.4 Treatment of gold electrodes with thiophenol
7.3.5 Hole mobility and contact resistance
7.3.6 Effect of bending on TFT
7.4 Speedier process of building large arrays of organic single crystals
7.4.1 The principle
7.4.2 The substrate
7.4.3 Coating the PVP dielectric layer on the gold film over the substrate
7.4.4 Fabrication of source/drain electrodes
7.4.5 Inking the PDMS stamp with OTS
7.4.6 Formation of OTS domains on the source/drain electrode pattern
7.4.7 Growth of organic single crystal
7.5 CuPc and F16CuPc TFTs on 15 μm diameter Au wire
7.5.1 PS dielectric deposition on OTS (octadecyltrichlorosilane)-modified silicon substrate
7.5.2 Synthesis of single-crystal CuPc and F16CuPc nanowires
7.5.3 Transfer of CuPc or F16CuPc nanowire onto PS
7.5.4 Source/drain electrodes on PS
7.5.5 Cleaning of Au wire
7.5.6 Transfer of the TFT to Au wire
7.5.7 CuPc and F16CuPc TFT characteristics
7.5.8 Complementary inverter
7.6 Discussion and conclusions
Review exercises
References
Chapter 8 Electrolyte-gated organic FET (EGOFET) and organic electrochemical FET (OECFET)
8.1 Introduction
8.2 Principle of electrolyte–gate organic FET (EGOFET)
8.2.1 Differentiating EGOFET from traditional OFET
8.2.2 Capacitive principle of operation
8.2.3 Effect of the high capacitance of the electrical double layer
8.3 Organic electrochemical TFT (OECFET)
8.3.1 Distinguishing OECFET from EGOFET
8.3.2 OECFET example
8.4 EGOFET and OECFET with water as gate dielectric
8.4.1 Formation of test patterns of source/drain electrodes on the PEN substrate
8.4.2 Fabrication of pentacene-based EGOFET
8.4.3 Fabrication of P3HT-based EGOFET
8.4.4 Fabrication of PEDOT:PSS-based OECFET
8.4.5 Formation of PDMS reservoir on all devices
8.4.6 Threshold voltage, transconductance and mobility values for different FETs
8.4.7 Signal–noise ratios and response times of FETs
8.5 Polyelectrolyte-gated EGOTFTs of different architectures
8.5.1 Fabrication of the structure: bottom gate with top contacts
8.5.2 Fabrication of the structure: top gate with bottom contacts
8.5.3 Fabrication of planar gate structure
8.5.4 Threshold voltage, on–off current ratio and field-effect mobility for the three structures
8.6 Vertical architecture OECFET
8.6.1 OECFET fabrication on PET substrate
8.6.2 OECFET fabrication on paper substrate
8.6.3 Switching times and current on–off ratios
8.7 Fiber-embedded EGOFET/OECFET for e-textiles
8.7.1 Creation of source/drain microgaps
8.7.2 Dip coating of P3HT over the source/drain gaps
8.7.3 Sewing gold wires on the P3HT film
8.7.4 Placement of electrolyte
8.7.5 Two stages of channel formation
8.8 Discussion and conclusions
Review exercises
References
Chapter 9 2D-material TFT
9.1 Introduction
9.2 Graphene TFT on polyimide
9.2.1 Capture–release process for PI film with gate electrode and h-BN dielectric
9.2.2 Synthesis of graphene film
9.2.3 Transferring graphene film from copper foil to polyimide by PMMA-assisted wet transfer process
9.2.4 Source/drain electrode deposition and electrical testing
9.2.5 TFT parameters
9.3 Graphene TFT on transparent PEN substrate
9.3.1 Bottom gate patterning and dielectric deposition
9.3.2 Graphene growth
9.3.3 Dry-transfer method for applying graphene over the gate
9.3.4 Source/drain electrodes and measurements
9.4 Graphene TFT on flexible glass
9.4.1 Specialties of flexible glass
9.4.2 Fabrication process
9.4.3 TFT parameters
9.5 MoS2 TFT on Kapton (polyimide)
9.5.1 TFT fabrication
9.5.2 TFT characteristics and bending effects
9.6 WS2 TFT on solution-cast PI substrate
9.6.1 Carrier wafer
9.6.2 Substrate
9.6.3 Deposition of gate electrode array
9.6.4 Gate dielectric deposition
9.6.5 Synthesis of WS2 for the active semiconductor layer
9.6.6 PMMA-assisted transferring of the WS2 triangles to the Al2O3 layer on the carrier wafer
9.6.7 Source/drain electrodes
9.6.8 Encapsulation
9.6.9 Mechanically peeling off the PI film with the overlying TFT
9.6.10 Static and multi-cycle bending effects
9.7 WSe2 TFT on a PET substrate
9.7.1 Mechanical exfoliation of WSe2 flakes
9.7.2 Graphene synthesis
9.7.3 Monolayer graphene transfer over WSe2 flakes
9.7.4 Creation of source–drain contact pads and hard mask for graphene etching
9.7.5 Dry etching of graphene in oxygen plasma
9.7.6 Photolithography to open windows for aluminum etching from graphene–WSe2 contact regions
9.7.7 Transfer of a few layers of h-BN to act as gate dielectric
9.7.8 Monolayer graphene transfer over h-BN for gate electrode formation
9.7.9 Photolithography for creating aluminum hard mask for gate electrode patterning
9.7.10 Dry etching of graphene
9.7.11 Removal of aluminum hard mask
9.7.12 TFT characteristics
9.8 Discussion and conclusions
Review exercises
References
Chapter 10 CNT FET
10.1 Introduction
10.2 High-mobility SWCNT TFT on spin-coated PI substrate
10.2.1 Substrate preparation
10.2.2 Formation of gate metal electrodes and contact pads
10.2.3 Gate dielectric deposition
10.2.4 Surface modification of SiO2 film for SWCNT deposition
10.2.5 Preparation of SWCNT solution
10.2.6 Deposition of random network of SWCNTs
10.2.7 Formation of source/drain contact pads
10.2.8 Peeling off the PI film
10.2.9 TFT characteristics
10.3 Semiconductor-enriched CNT-based TFT on spin-coated PI substrate for active-matrix backplane
10.3.1 Substrate used
10.3.2 Gate structure
10.3.3 SWCNT network deposition
10.3.4 Source–drain metallization and encapsulation
10.3.5 Removing the PI film from the wafer
10.3.6 Electrical properties of TFT
10.3.7 Stretchability of PI substrate
10.4 CNT TFT with high current on–off ratio on a Kapton substrate
10.4.1 Substrate preparation and mounting
10.4.2 Gate electrode formation
10.4.3 Gate dielectric deposition
10.4.4 Al2O3 surface modification
10.4.5 CNT deposition
10.4.6 Source/drain contacts
10.4.7 TFT behavior
10.5 Inkjet printed SWCNT TFT on PES substrate
10.5.1 Substrate functionalization
10.5.2 SWCNT deposition
10.5.3 Source–drain electrode printing
10.5.4 Channel area definition
10.5.5 Gate dielectric deposition
10.5.6 Gate electrode printing
10.5.7 TFT parameters
10.6 All-inkjet printed 5 GHz CNT TFT on Kapton polyimide film
10.6.1 Printing source/drain electrodes on Kapton
10.6.2 Printing active carrier transport layer
10.6.3 Printing gate dielectric
10.6.4 Printing the top gate electrode
10.6.5 TFT performance
10.7 Gravure printed SWCNT-based TFT for D flip–flop, half-adder and full-adder on PET foil
10.7.1 D flip–flop
10.7.2 Half- and full-adders
10.8 Inverse gravure-printed CNT TFT on a PET substrate with solution-deposited SWCNTs
10.8.1 Substrate cleaning and surface functionalization
10.8.2 Deposition of active channel material
10.8.3 Source–drain electrode printing
10.8.4 Gate dielectric printing
10.8.5 Removal of excess SWCNTs
10.8.6 Gate electrode printing
10.8.7 TFT properties
10.9 All-CNT TFT on PEN substrate using a photosensitive dry film
10.9.1 CNT synthesis for gate/source/drain electrodes
10.9.2 Preparation of high-purity semiconducting CNT suspension for channel region
10.9.3 Creation of an alignment mark on the PEN substrate
10.9.4 Transfer of CNT film for source/drain electrodes to PEN substrate
10.9.5 Lamination of substrate with photosensitive dry film
10.9.6 Patterning and etching of source/drain electrodes and interconnections
10.9.7 Deposition of semiconducting CNTs
10.9.8 Patterning of the semiconducting CNT film
10.9.9 Deposition of gate insulator
10.9.10 Formation of contact windows in PMMA
10.9.11 Transfer of gate electrodes
10.9.12 Electrical performance of TFT
10.10 Discussion and conclusions
Review exercises
References
Chapter 11 Nanowire FET
11.1 Introduction
11.2 Ge/Si NW FET on PI film
11.2.1 Substrate
11.2.2 Growth of Ge/Si core/shell NWs
11.2.3 Contact printing of NWs on the substrate
11.2.4 Source/drain electrode formation
11.2.5 Gate dielectric and electrode deposition
11.2.6 Passivation and via hole etching
11.2.7 Peeling off the flexible circuit
11.2.8 Electrical performance and mechanical flexibility
11.2.9 Upscaling of the process
11.3 P-type Si/SiO2 NW TFT on PEEK
11.3.1 Synthesis of P-type single-crystal silicon NWs
11.3.2 NW growth apparatus
11.3.3 Preparation of NW growth substrates
11.3.4 NW growth parameters
11.3.5 Alternative laser ablation method of NW synthesis
11.3.6 Directed flow assembly of Si NWs
11.3.7 TFT fabrication with NWs
11.4 P-type Si/SiO2 NW TFT on Mylar
11.4.1 TFT fabrication
11.4.2 Electrical and bending characteristics of TFT
11.5 TFT on a PET substrate by the SNAP NW transfer approach
11.5.1 Limitations of photolithographic methods of making NWs
11.5.2 Superlattice nanowire pattern (SNAP) transfer technique
11.5.3 Producing a Pt-coated superlattice edge
11.5.4 Making SOI wafer ready to receive Pt NWs
11.5.5 Transferring Pt NWs to doped SOI wafer
11.5.6 Reactive ion etching of silicon
11.5.7 Dissolving platinum NWs to release the Si NWs
11.5.8 Residual epoxy removal
11.5.9 Retrieval of NW array by PDMS
11.5.10 Plastic substrate preparation for receiving Si NWs
11.5.11 Harvesting Si NWs on the PET substrate from PDMS slab
11.5.12 Forming source/drain electrodes for completing the bottom-gate TFT
11.5.13 Sectioning the geometry into device islands
11.5.14 Constructing the top-gate TFT
11.5.15 Top-gate TFT characteristics
11.6 Discussion and conclusions
Review exercises
References