Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream: 12th International Conference, FPL 2002 Montpellier, France, September 2–4, 2002 Proceedings

The Age of Adaptive Computing Is Here....Pages 1-3
Disruptive Trends by Data-Stream-Based Computing....Pages 4-4
Multithreading for Logic-Centric Systems....Pages 5-14
Fast Prototyping with Co-operation of Simulation and Emulation....Pages 15-25
How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project....Pages 26-35
Implementing Asynchronous Circuits on LUT Based FPGAs....Pages 36-46
A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations....Pages 47-58
Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems....Pages 59-68
iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications....Pages 69-78
Field-Programmable Custom Computing Machines - A Taxonomy -....Pages 79-88
Embedded Reconfigurable Logic Core for DSP Applications....Pages 89-101
Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard....Pages 102-111
FPGA QAM Demodulator Design....Pages 112-121
Analytical Framework for Switch Block Design....Pages 122-131
Modular, Fabric-Specific Synthesis for Programmable Architectures....Pages 132-141
On Optimum Designs of Universal Switch Blocks....Pages 142-151
Improved Functional Simulation of Dynamically Reconfigurable Logic....Pages 152-161
Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology....Pages 162-170
Dynamic Reconfiguration in Mobile Systems....Pages 171-181
Using PARBIT to Implement Partial Run-Time Reconfigurable Systems....Pages 182-191
Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs....Pages 192-201
Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models....Pages 202-211
FPGA Implementation of the Wavelet Packet Transform for High Speed Communications....Pages 212-221
A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBits™....Pages 222-231
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices....Pages 232-241
Rapid and Reliable Routability Estimation for FPGAs....Pages 242-252
Integrated Iterative Approach to FPGA Placement....Pages 253-262
TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs....Pages 263-270
High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices....Pages 271-280
High Speed Homology Search Using Run-Time Reconfiguration....Pages 281-291
Partially Reconfigurable Cores for Xilinx Virtex....Pages 292-301
On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs....Pages 302-311
A Flexible Power Model for FPGAs....Pages 312-321
A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs....Pages 322-331
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor....Pages 332-339
A Tool for Activity Estimation in FPGAs....Pages 340-349
FSM Decomposition for Low Power in FPGA....Pages 350-359
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search....Pages 360-369
A Prolog-Based Hardware Development Environment....Pages 370-380
Fly — A Modifiable Hardware Compiler....Pages 381-390
Challenges and Opportunities for FPGA Platforms....Pages 391-392
Design and Implementation of FPGA Circuits for High Speed Network Monitors....Pages 393-403
Granidt: Towards Gigabit Rate Network Intrusion Detection Technology....Pages 404-413
Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques....Pages 414-423
Field-Programmable Analog Arrays: A Floating—Gate Approach....Pages 424-433
A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model....Pages 434-443
A Framework for Teaching (Re)Configurable Architectures in Student Projects....Pages 444-451
Specialized Hardware for Deep Network Packet Filtering....Pages 452-461
Implementation of a Successive Erasure BCH (16,7,6) Decoder and Performance Simulation by Rapid Prototyping....Pages 462-471
Fast RNS FPL-based Communications Receiver Design and Implementation....Pages 472-481
UltraSONIC: A Reconfigurable Architecture for Video Image Processing....Pages 482-491
Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA....Pages 492-502
Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA....Pages 503-512
Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices....Pages 513-522
Automating Customisation of Floating-Point Designs....Pages 523-533
Energy-Efficient Matrix Multiplication on FPGAs....Pages 534-544
Run-Time Adaptive Flexible Instruction Processors....Pages 545-555
DARP — A Digital Audio Reconfigurable Processor....Pages 556-566
System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors....Pages 567-576
An FPGA Based SHA-256 Processor....Pages 577-585
Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension....Pages 586-595
On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs....Pages 596-606
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs....Pages 607-615
Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs....Pages 616-626
Logarithmic Number System and Floating-Point Arithmetics on FPGA....Pages 627-636
Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture....Pages 637-646
Morphable Multipliers....Pages 647-656
A Library of Parameterized Floating-Point Modules and Their Use....Pages 657-666
Wordlength as an Architectural Parameter for Reconfigurable Computing Devices....Pages 667-676
An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms....Pages 677-686
Introducing ReConfigME: An Operating System for Reconfigurable Computing....Pages 687-697
Efficient Metacomputation Using Self-Reconfiguration....Pages 698-709
An FPGA Co-processor for Real-Time Visual Tracking....Pages 710-719
Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware....Pages 720-729
Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing....Pages 730-739
Parallel FPGA Implementation of the Split and Merge Discrete Wavelet Transform....Pages 740-749
Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2 m )....Pages 750-759
6.78 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm....Pages 760-769
Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform....Pages 770-779
A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation....Pages 780-789
Creating a World of Smart Re-configurable Devices....Pages 790-794
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs....Pages 795-805
Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System....Pages 806-815
The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance....Pages 816-825
An FPGA Implementation of a Multi-comparand Multi-search Associative Processor....Pages 826-835
AES Implementation on FPGA: Time - Flexibility Tradeoff....Pages 836-844
An FPGA Implementation of the Linear Cryptanalysis....Pages 845-852
Compiling Application-Specific Hardware....Pages 853-863
XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture....Pages 864-874
Sea Cucumber: A Synthesizing Compiler for FPGAs....Pages 875-885
Practical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAs....Pages 886-896
Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs....Pages 897-904
High Performance Quadrature Digital Mixers for FPGAs....Pages 905-914
HAGAR: Efficient Multi-context Graph Processors....Pages 915-924
Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform....Pages 925-934
On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach....Pages 935-944
REFLIX: A Processor Core for Reactive Embedded Applications....Pages 945-954
Factors Influencing the Performance of a CPU-RFU Hybrid Architecture....Pages 955-965
Implementing Converters in FPLD....Pages 966-975
A Quantitative Understanding of the Performance of Reconfigurable Coprocessors....Pages 976-986
Integration of Reconfigurable Hardware into System-Level Design....Pages 987-996
A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures....Pages 997-1006
The Integration of SystemC and Hardware-Assisted Verification....Pages 1007-1016
Using Design Hierarchy to Improve Quality of Results in FPGAs....Pages 1017-1026
Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations....Pages 1027-1036
A General Hardware Design Model for Multicontext FPGAs....Pages 1037-1047
Dynamically Reconfigurable Hardware — A New Perspective for Neural Network Implementations....Pages 1048-1057
A Compilation Framework for a Dynamically Reconfigurable Architecture....Pages 1058-1067
Data Dependent Circuit for Subgraph Isomorphism Problem....Pages 1068-1071
Exploration of Design Space in ECDSA....Pages 1072-1075
2D and 3D Computer Graphics Algorithms under MORPHOSYS....Pages 1076-1079
A HIPERLAN/2 — IEEE 802.11a Reconfigurable System-on-Chip....Pages 1080-1083
SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor....Pages 1084-1087
Real-Time Medical Diagnosis on a Multiple FPGA-based System....Pages 1088-1091
Threshold Element-Based Symmetric Function Generators and Their Functional Extension....Pages 1092-1096
Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks....Pages 1097-1100
Building Custom FIR Filters Using System Generator....Pages 1101-1104
SoC Based Low Cost Design of Digital Audio Broadcasting Transport Network Applications....Pages 1105-1109
Dynamic Constant Coefficient Convolvers Implemented in FPGAs....Pages 1110-1113
VIZARD II: An FPGA-based Interactive Volume Rendering System....Pages 1114-1117
RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing....Pages 1118-1121
General Purpose Prototyping Platform for Data-Processor Research and Development....Pages 1122-1125
High Speed Computation of Three Dimensional Cellular Automata with FPGA....Pages 1126-1130
SOPC-based Embedded Smart Strain Gage Sensor....Pages 1131-1134
Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications....Pages 1135-1138
An FPGA-based Node Controller for a High Capacity WDM Optical Packet Network....Pages 1139-1143
FPGA and Mixed FPGA-DSP Implementations of Electrical Drive Algorithms....Pages 1144-1147
Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer....Pages 1148-1151
A Novel Watermarking Technique for LUT Based FPGA Designs....Pages 1152-1155
Implementing CSAT Local Search on FPGAs....Pages 1156-1159
A Reconfigurable Processor Architecture....Pages 1160-1163
A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor....Pages 1164-1167
Gene Matching Using JBits....Pages 1168-1171
Massively Parallel/Reconfigurable Emulation Model for the D-algorithm....Pages 1172-1176
A Placement/Routing Approach for FPGA Accelerators....Pages 1177-1181