This book contains the papers presented at the 9th International Workshop on Field ProgrammableLogic and Applications (FPL’99), hosted by the University of Strathclyde in Glasgow, Scotland, August 30 – September 1, 1999. FPL’99 is the ninth in the series of annual FPL workshops. The FPL’99 programme committee has been fortunate to have received a large number of high-quality papers addressing a wide range of topics. From these, 33 papers have been selected for presentation at the workshop and a further 32 papers have been accepted for the poster sessions. A total of 65 papers from 20 countries are included in this volume. FPL is a subject area that attracts researchers from both electronic engine- ing and computer science. Whether we are engaged in research into soft ha- ware or hard software seems to be primarily a question of perspective. What is unquestionable is that the interaction of groups of researchers from di?erent backgrounds results in stimulating and productive research. As we prepare for the new millennium, the premier European forum for - searchers in ?eld programmable logic remains the FPL workshop. Next year the FPL series of workshopswill celebrate its tenth anniversary.The contribution of so many overseas researchers has been a particularly attractive feature of these events, giving them a truly international perspective, while the informal and convivial atmosphere that pervades the workshops have been their hallmark. We look forward to preserving these features in the future while continuing to expand the size and quality of the events.
Author(s): Paul Graham, Brent Nelson (auth.), Patrick Lysaght, James Irvine, Reiner Hartenstein (eds.)
Series: Lecture Notes in Computer Science 1673
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 1999
Language: English
Pages: 552
Tags: Logic Design; Arithmetic and Logic Structures; Processor Architectures; Complexity
Front Matter....Pages -
Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing....Pages 1-10
Auditory Signal Processing in Hardware....Pages 11-20
SONIC – A Plug-In Architecture for Video Processing....Pages 21-30
DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems....Pages 31-40
Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems Using the DCS CAD Framework....Pages 41-50
Optimal Finite Field Multipliers for FPGAs....Pages 51-60
Memory Access Optimization and RAM Inference for Pipeline Vectorization....Pages 61-70
Analysis and Optimization of 3-D FPGA Design Parameters....Pages 71-80
Tabu Search: Ultra-Fast Placement for FPGAs....Pages 81-90
Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies....Pages 91-100
Hierarchical Interactive Approach to Partition Large Designs into FPGAs....Pages 101-110
Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays....Pages 111-123
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems....Pages 124-133
A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic....Pages 134-143
Self Controlling Dynamic Reconfiguration: A Case Study....Pages 144-154
An Internet Based Development Framework for Reconfigurable Computing....Pages 155-164
On Tool Integration in High-Performance FPGA Design Flows....Pages 165-174
Hardware-Software Codesign for Dynamically Reconfigurable Architectures....Pages 175-184
Serial Hardware Libraries for Reconfigurable Designs....Pages 185-194
Reconfigurable Computing in Remote and Harsh Environments....Pages 195-204
Communication Synthesis for Reconfigurable Embedded Systems....Pages 205-214
Run-Time Parameterizable Cores....Pages 215-222
Rendering PostScript TM Fonts on FPGAs....Pages 223-232
Implementing PhotoShop TM Filters in Virtex TM ....Pages 233-242
Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler....Pages 243-252
Quantitative Analysis of Run-Time Reconfigurable Database Search....Pages 253-263
An On-Line Arithmetic Based FPGA for Low-Power Custom Computing....Pages 264-273
A New Switch Block for Segmented FPGAs....Pages 274-281
PulseDSP – A Signal Processing Oriented Programmable Architecture....Pages 282-290
FPGA Viruses....Pages 291-300
Genetic Programming Using Self-Reconfigurable FPGAs....Pages 301-312
Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs....Pages 313-322
Synthia : Synthesis of Interacting Automata Targeting LUT-based FPGAs....Pages 323-332
An FPGA-Based Prototyping System for Real-Time Verification of Video Processing Schemes....Pages 333-338
An FPGA Implementation of Goertzel Algorithm....Pages 339-346
Pipelined Multipliers and FPGA Architectures....Pages 347-352
FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding....Pages 353-358
Reconfigurable Multiplier for Virtex FPGA Family....Pages 359-364
Pipelined Floating Point Arithmetic Optimised for FPGA Architectures....Pages 365-370
SL – A Structural Hardware Design Language....Pages 371-376
High-Level Hierarchical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules....Pages 377-384
Mapping Applications onto Reconfigurable KressArrays....Pages 385-390
Global Routing Models....Pages 391-395
Power Modelling in Field Programmable Gate Arrays (FPGA)....Pages 396-404
NEBULA: A Partially and Dynamically Reconfigurable Architecture....Pages 405-410
High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects....Pages 411-416
AHA-GRAPE: Adaptive Hydrodynamic Architecture – GRAvity PipE....Pages 417-424
DIME – The First Module Standard for FPGA Based High Performance Computing....Pages 425-430
The Proteus Processor — A Conventional CPU with Reconfigurable Functionality....Pages 431-437
Logic Circuit Speeding up through Multiplexing....Pages 438-443
A Wildcarding Mechanism for Acceleration of Partial Configurations....Pages 444-449
Hardware Implementation Techniques for Recursive Calls and Loops....Pages 450-455
A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation....Pages 456-461
An Alternative Solution for Reconfigurable Coprocessors Hardware and Interface Synthesis....Pages 462-468
Reconfigurable Programming in the Large on Extendable Uniform Reconfigurable Computing Array’s: An Integrated Approach Based on Reconfigurable Virtual Architectures....Pages 469-474
A Concept for an Evaluation Framework for Reconfigurable Systems....Pages 475-480
Debugging Application-Specific Programmable Products....Pages 481-486
IP Validation for FPGAs Using Hardware Object Technology TM ....Pages 487-494
A Processor for Artificial Life Simulation....Pages 495-500
A Distributed, Scalable, Multi-layered Approach to Evolvable System Design Using FPGA’s....Pages 501-506
Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching....Pages 507-513
A Reconfigurable Architecture for High Speed Computation by Pipeline Processing....Pages 514-519
Seeking (the Right) Problems for the Solutions of Reconfigurable Computing....Pages 520-525
A Runtime Reconfigurable Implementation of the GSAT Algorithm....Pages 526-531
Accelerating Boolean Implications with FPGAs....Pages 532-537
Back Matter....Pages -
