This book constitutes the refereed proceedings of the 7th International Workshop on Field Programmable Logic and Applications, FPL '97, held in London, UK, in September 1997. The 51 revised full papers in the volume were carefully selected from a large number of high-quality papers. The book is divided into sections on devices and architectures, devices and systems, reconfiguration, design tools, custom computing and codesign, signal processing, image and video processing, sensors and graphics, color and robotics, and applications.
Author(s): Julio Faura, Juan Manuel Moreno (auth.), Wayne Luk, Peter Y. K. Cheung, Manfred Glesner (eds.)
Series: Lecture Notes in Computer Science 1304
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 1997
Language: English
Pages: 512
Tags: Computer Hardware; Systems and Information Theory in Engineering; Mathematical Logic and Formal Languages
Multicontext dynamic reconfiguration and real-time probing on a novel mixed signal programmable device with on-chip microprocessor....Pages 1-10
CAD-oriented FPGA and dedicated CAD system for telecommunications....Pages 11-20
Rothko: A three dimensional FPGA architecture, its fabrication, and design tools....Pages 21-30
Extending dynamic circuit switching to meet the challenges of new FPGA architectures....Pages 31-40
Performance evaluation of a full speed PCI initiator and target subsystem using FPGAs....Pages 41-50
Implementation of pipelined multipliers on Xilinx FPGAs....Pages 51-60
The XC620ODS development system....Pages 61-68
Thermal monitoring on FPGAs using ring-oscillators....Pages 69-78
A reconfigurable approach to low cost media processing....Pages 79-90
Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research....Pages 91-100
Stream synthesis for a wormhole run-time reconfigurable platform....Pages 101-110
Pipeline morphing and virtual pipelines....Pages 111-120
Parallel graph colouring using FPGAs....Pages 121-130
Run-time compaction of FPGA designs....Pages 131-140
Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement....Pages 141-150
A case study of partially evaluated hardware circuits: Key-specific DES....Pages 151-160
Run-time parameterised circuits for the Xilinx XC6200....Pages 161-172
Automatic identification of swappable logic units in XC6200 circuitry....Pages 173-182
Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic....Pages 183-192
Exploiting reconfigurability through domain-specific systems....Pages 193-202
Technology mapping by binate covering....Pages 203-212
VPR: a new packing, placement and routing tool for FPGA research....Pages 213-222
Technology mapping of heterogeneous LUT-based FPGAs....Pages 223-234
Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs....Pages 235-244
Technology mapping of LUT based FPGAs for delay optimisation....Pages 245-254
Automatic Mapping of Algorithms onto multiple FPGA-SRAM Modules....Pages 255-264
FPLD HDL synthesis employing high-level evolutionary algorithm optimisation....Pages 265-273
An hardware/software partitioning algorithm for custom computing machines....Pages 274-283
The Java Environment for Reconfigurable Computing....Pages 284-293
Data scheduling to increase performance of parallel accelerators....Pages 294-303
An operating system for custom computing machines based on the Xputer paradigm....Pages 304-313
Fast parallel implementation of DFT using configurable devices....Pages 314-323
Enhancing fixed point DSP processor performance by adding CPLD's as coprocessing elements....Pages 324-332
A case study of algorithm implementation in reconfigurable hardware and software....Pages 333-343
A reconfigurable data-localised array for morphological algorithms....Pages 344-353
Virtual radix array processors (V-RaAP)....Pages 354-363
An FPGA implementation of a matched filter detector for spread spectrum communications systems....Pages 364-373
An NTSC and PAL closed caption processor....Pages 374-381
A 800Mpixel/sec reconfigurable image correlator on XC6216....Pages 382-391
A reconfigurable coprocessor for a PCI-based real time computer vision system....Pages 392-399
Real-time stereopsis using FPGAs....Pages 400-409
FPGAs Implementation of a digital IQ demodulator using VHDL....Pages 410-417
Hardware compilation, configurable platforms and ASICs for self-validating sensors....Pages 418-427
PostScript™ rendering with virtual hardware....Pages 428-437
P4: A platform for FPGA implementation of protocol boosters....Pages 438-447
Satisfiability on reconfigurable hardware....Pages 448-456
Auto-configurable array for GCD computation....Pages 457-461
Structural versus algorithmic approaches for efficient adders on xilinx 5200 FPGA....Pages 462-471
FPGA implementation of real-time digital controllers using on-line arithmetic....Pages 472-481
A prototyping environment for fuzzy controllers....Pages 482-490
A reconfigurable sensor-data processing system for personal robots....Pages 491-500
