This book constitutes the refereed proceedings of the 11th International Conference on Field-Programmable Logic and Application, FPL 2001, held in Belfast, Northern Ireland, UK, in August 2001.
The 56 revised full papers and 15 short papers presented were carefully reviewed and selected from a total of 117 submissions. The book offers topical sections on architectural framework, place and route, architecture, DSP, synthesis, encryption, runtime reconfiguration, graphics and vision, networking, processor interaction, applications, methodology, loops and systolic, image processing, faults, and arithmetic.
Author(s): Michael J. Flynn, Albert A. Liddicoat (auth.), Gordon Brebner, Roger Woods (eds.)
Series: Lecture Notes in Computer Science 2147
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2001
Language: English
Pages: 665
Tags: Logic Design; Processor Architectures; Computer Communication Networks; Computer-Aided Engineering (CAD, CAE) and Design
Technology Trends and Adaptive Computing....Pages 1-5
Prototyping Framework for Reconfigurable Processors....Pages 6-16
An Emulator for Exploring RaPiD Configurable Computing Architectures....Pages 17-26
A New Placement Method for Direct Mapping into LUT-Based FPGAs....Pages 27-36
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits....Pages 37-47
Macrocell Architectures for Product Term Embedded Memory Arrays....Pages 48-58
Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs....Pages 59-69
Memory Synthesis for FPGA-Based Reconfigurable Computers....Pages 70-80
Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic....Pages 81-90
Implementation of (Normalised) RLS Lattice on Virtex....Pages 91-100
Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing....Pages 101-111
Static Profile-Driven Compilation for FPGAs....Pages 112-122
Synthesizing RTL Hardware from Java Byte Codes....Pages 123-132
PuMA ++: From Behavioral Specification to Multi-FPGA-Prototype....Pages 133-141
Secure Configuration of Field Programmable Gate Arrays....Pages 142-151
Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm....Pages 152-161
JBits™ Implementations of the Advanced Encryption Standard (Rijndael)....Pages 162-171
Task-Parallel Programming of Reconfigurable Systems....Pages 172-181
Chip-Based Reconfigurable Task Management....Pages 182-191
Configuration Caching and Swapping....Pages 192-202
Multiple Stereo Matching Using an Extended Architecture....Pages 203-212
Implementation of a NURBS to Bézier Conversor with Constant Latency....Pages 213-222
Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems....Pages 223-231
Processing Models for the Next Generation Network....Pages 232-232
Tightly Integrated Placement and Routing for FPGAs....Pages 233-242
Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays....Pages 243-253
Reconfigurable Router Modules Using Network Protocol Wrappers....Pages 254-263
Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware....Pages 264-274
The MOLEN ρμ-Coded Processor....Pages 275-285
Run-Time Optimized Reconfiguration Using Instruction Forecasting....Pages 286-295
CRISP: A Template for Reconfigurable Instruction Set Processors....Pages 296-305
Evaluation of an FPGA Implementation of the Discrete Element Method....Pages 306-314
Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers....Pages 315-325
A Reconfigurable Embedded Input Device for Kinetically Challenged Persons....Pages 326-335
Bubble Partitioning for LUT-Based Sequential Circuits....Pages 336-345
Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits....Pages 346-356
Placing, Routing, and Editing Virtual FPGAs....Pages 357-366
Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver....Pages 367-376
A Music Synthesizer on FPGA....Pages 377-387
Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders....Pages 388-397
Loop Tiling for Reconfigurable Accelerators....Pages 398-408
The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems....Pages 409-419
A n -Bit Reconfigurable Scalar Quantiser....Pages 420-429
Real Time Morphological Image Contrast Enhancement in Virtex FPGA....Pages 430-440
Demonstrating Real-time JPEG Image Compression-Decompression using Standard Component IP Cores on a Programmable Logic based Platform for DSP and Image Processing....Pages 441-450
Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware....Pages 451-460
The Evolution of Programmable Logic: Past, Present, and Future Predictions....Pages 461-461
Dynamically Reconfigurable Cores....Pages 462-472
Reconfigurable Breakpoints for Co-debug....Pages 473-482
Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification....Pages 483-492
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits....Pages 493-502
A Generic Library for Adaptive Computing Environments....Pages 503-512
Generative Development System for FPGA essors with Active Components ....Pages 513-522
Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines....Pages 523-533
System Level Tools for DSP in FPGAs....Pages 534-543
Parameterized Function Evaluation for FPGAs....Pages 544-554
Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures....Pages 555-564
A Digit-Serial Structure for Reconfigurable Multipliers....Pages 565-573
FPGA Resource Reduction Through Truncated Multiplication....Pages 574-583
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures....Pages 584-589
An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars....Pages 590-594
Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach....Pages 595-600
An Approach to Real-Time Visualization of PIV Method with FPGA....Pages 601-606
FPGA-Based Discrete Wavelet Transforms System....Pages 607-612
X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor....Pages 613-617
Arithmetic Operation Oriented Reconfigurable Chip: RHW....Pages 618-622
Initial Analysis of the Proteus Architecture....Pages 623-627
Building Asynchronous Circuits with JBits....Pages 628-632
Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux....Pages 633-637
A Reconfigurable Approach to Packet Filtering....Pages 638-642
FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding....Pages 643-647
A Data Re-use Based Compiler Optimization for FPGAs....Pages 648-652
Dijkstra’s Shortest Path Routing Algorithm in Reconfigurable Hardware....Pages 653-657
A System on Chip for Power Line Communications According to European Home Systems Specifications....Pages 658-662
